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| #define SSP_CPHA_FIRST ((uint32_t)(0)) |
SSP configuration parameter definesClock phase control bit
Definition at line 49 of file lpc17xx_ssp.h.
| #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND |
Definition at line 50 of file lpc17xx_ssp.h.
| #define SSP_CPOL_HI ((uint32_t)(0)) |
Clock polarity control bit
Definition at line 60 of file lpc17xx_ssp.h.
| #define SSP_CPOL_LO SSP_CR0_CPOL_HI |
Definition at line 61 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_10 SSP_CR0_DSS(10) |
Databit number = 10
Definition at line 74 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_11 SSP_CR0_DSS(11) |
Databit number = 11
Definition at line 75 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_12 SSP_CR0_DSS(12) |
Databit number = 12
Definition at line 76 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_13 SSP_CR0_DSS(13) |
Databit number = 13
Definition at line 77 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_14 SSP_CR0_DSS(14) |
Databit number = 14
Definition at line 78 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_15 SSP_CR0_DSS(15) |
Databit number = 15
Definition at line 79 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_16 SSP_CR0_DSS(16) |
Databit number = 16
Definition at line 80 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_4 SSP_CR0_DSS(4) |
SSP data bit number defines Databit number = 4
Definition at line 68 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_5 SSP_CR0_DSS(5) |
Databit number = 5
Definition at line 69 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_6 SSP_CR0_DSS(6) |
Databit number = 6
Definition at line 70 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_7 SSP_CR0_DSS(7) |
Databit number = 7
Definition at line 71 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_8 SSP_CR0_DSS(8) |
Databit number = 8
Definition at line 72 of file lpc17xx_ssp.h.
| #define SSP_DATABIT_9 SSP_CR0_DSS(9) |
Databit number = 9
Definition at line 73 of file lpc17xx_ssp.h.
| #define SSP_DMA_RX SSP_DMA_RXDMA_EN |
SSP DMA definesSSP bit for enabling RX DMA
Definition at line 154 of file lpc17xx_ssp.h.
| #define SSP_DMA_TX SSP_DMA_TXDMA_EN |
SSP bit for enabling TX DMA
Definition at line 156 of file lpc17xx_ssp.h.
| #define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE |
National Micro-wire mode
Definition at line 88 of file lpc17xx_ssp.h.
| #define SSP_FRAME_SPI SSP_CR0_FRF_SPI |
SSP Frame Format definition Motorola SPI mode
Definition at line 84 of file lpc17xx_ssp.h.
| #define SSP_FRAME_TI SSP_CR0_FRF_TI |
TI synchronous serial mode
Definition at line 86 of file lpc17xx_ssp.h.
| #define SSP_INTCFG_ROR SSP_IMSC_ROR |
SSP Interrupt Configuration definesReceive Overrun
Definition at line 108 of file lpc17xx_ssp.h.
| #define SSP_INTCFG_RT SSP_IMSC_RT |
Receive TimeOut
Definition at line 110 of file lpc17xx_ssp.h.
| #define SSP_INTCFG_RX SSP_IMSC_RX |
Rx FIFO is at least half full
Definition at line 112 of file lpc17xx_ssp.h.
| #define SSP_INTCFG_TX SSP_IMSC_TX |
Tx FIFO is at least half empty
Definition at line 114 of file lpc17xx_ssp.h.
| #define SSP_INTCLR_ROR SSP_ICR_ROR |
SSP Interrupt Clear defines Writing a 1 to this bit clears the "frame was received when RxFIFO was full" interrupt
Definition at line 145 of file lpc17xx_ssp.h.
| #define SSP_INTCLR_RT SSP_ICR_RT |
Writing a 1 to this bit clears the "Rx FIFO was not empty and has not been read for a timeout period" interrupt
Definition at line 148 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR |
SSP Raw Interrupt Status definesReceive Overrun
Definition at line 132 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_RAW_RT SSP_RIS_RT |
Receive TimeOut
Definition at line 134 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_RAW_RX SSP_RIS_RX |
Rx FIFO is at least half full
Definition at line 136 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_RAW_TX SSP_RIS_TX |
Tx FIFO is at least half empty
Definition at line 138 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_ROR SSP_MIS_ROR |
SSP Configured Interrupt Status definesReceive Overrun
Definition at line 120 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_RT SSP_MIS_RT |
Receive TimeOut
Definition at line 122 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_RX SSP_MIS_RX |
Rx FIFO is at least half full
Definition at line 124 of file lpc17xx_ssp.h.
| #define SSP_INTSTAT_TX SSP_MIS_TX |
Tx FIFO is at least half empty
Definition at line 126 of file lpc17xx_ssp.h.
| #define SSP_MASTER_MODE ((uint32_t)(0)) |
Definition at line 65 of file lpc17xx_ssp.h.
| #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN |
SSP master mode enable
Definition at line 64 of file lpc17xx_ssp.h.
| #define SSP_STAT_BUSY SSP_SR_BSY |
SSP status SSP Busy bit
Definition at line 102 of file lpc17xx_ssp.h.
| #define SSP_STAT_DONE (1UL<<8) |
Done
Definition at line 159 of file lpc17xx_ssp.h.
| #define SSP_STAT_ERROR (1UL<<9) |
Error
Definition at line 160 of file lpc17xx_ssp.h.
| #define SSP_STAT_RXFIFO_FULL SSP_SR_RFF |
SSP status RX FIFO full bit
Definition at line 100 of file lpc17xx_ssp.h.
| #define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE |
SSP status RX FIFO not empty bit
Definition at line 98 of file lpc17xx_ssp.h.
| #define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE |
SSP Status definesSSP status TX FIFO Empty bit
Definition at line 94 of file lpc17xx_ssp.h.
| #define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF |
SSP status TX FIFO not full bit
Definition at line 96 of file lpc17xx_ssp.h.
1.8.4 
