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uc-sdk
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| ADC Init structure definition | |
| Analog to Digital Converter | |
| Acceptance Filter Section Table structure | |
| Alternate Function I/O | |
| Backup Registers | |
| Controller Area Network FIFOMailBox | |
| CAN filter init structure definition | |
| Controller Area Network FilterRegister | |
| CAN init structure definition | |
| CAN message object structure | |
| Pin Configuration structure | |
| Controller Area Network TxMailBox | |
| Controller Area Network | |
| CAN Rx message structure definition | |
| CAN Tx message structure definition | |
| CEC Init structure definition | |
| Consumer Electronics Control (CEC) | |
| Core Debug register structure definition | |
| CRC calculation unit | |
| Configuration for DAC converter control register | |
| DAC Init structure definition | |
| Digital to Analog Converter | |
| Debug MCU | |
| DMA Controller | |
| DMA Init structure definition | |
| Extended ID Frame Format Entry structure | |
| Group of Extended ID Frame Format Entry structure | |
| EMAC configuration structure definition | |
| TX Data Buffer structure definition | |
| Ethernet MAC | |
| EXTI Initialize structure | |
| External Interrupt/Event Controller | |
| FLASH Registers | |
| Flexible Static Memory Controller | |
| Flexible Static Memory Controller Bank1E | |
| Flexible Static Memory Controller Bank2 | |
| Flexible Static Memory Controller Bank3 | |
| Flexible Static Memory Controller Bank4 | |
| Timing parameters For FSMC NAND and PCCARD Banks | |
| FSMC NAND Init structure definition | |
| FSMC NOR/SRAM Init structure definition | |
| Timing parameters For NOR/SRAM Banks | |
| FSMC PCCARD Init structure definition | |
| FullCAN Entry structure | |
| GPDMA Channel configuration structure type definition | |
| GPDMA Linker List Item structure type definition | |
| Fast GPIO port byte type definition | |
| Fast GPIO port half-word type definition | |
| GPIO Init structure definition | |
| General Purpose I/O | |
| I2C Init structure definition | |
| Master transfer setup data structure definitions | |
| I2C Own slave address setting structure | |
| Slave transfer setup data structure definitions | |
| Inter Integrated Circuit Interface | |
| I2S configuration structure definition | |
| I2S DMA configuration structure definition | |
| I2S Init structure definition | |
| I2S mode configuration structure definition | |
| Instrumentation Trace Macrocell (ITM) register structure definition | |
| Instrumentation Trace Macrocell (ITM) register structure definition | |
| Independent WATCHDOG | |
| Analog-to-Digital Converter (ADC) register structure definition | |
| Controller Area Network Controller (CAN) register structure definition | |
| Controller Area Network Acceptance Filter RAM (CANAF_RAM)structure definition | |
| Controller Area Network Acceptance Filter(CANAF) register structure definition | |
| Controller Area Network Central (CANCR) register structure definition | |
| Digital-to-Analog Converter (DAC) register structure definition | |
| Ethernet Media Access Controller (EMAC) register structure definition | |
| General Purpose Direct Memory Access (GPDMA) register structure definition | |
| General Purpose Direct Memory Access Channel (GPDMACH) register structure definition | |
| General Purpose Input/Output (GPIO) register structure definition | |
| General Purpose Input/Output interrupt (GPIOINT) register structure definition | |
| Inter-Integrated Circuit (I2C) register structure definition | |
| Inter IC Sound (I2S) register structure definition | |
| Motor Control Pulse-Width Modulation (MCPWM) register structure definition | |
| Pin Connect Block (PINCON) register structure definition | |
| Pulse-Width Modulation (PWM) register structure definition | |
| Quadrature Encoder Interface (QEI) register structure definition | |
| Repetitive Interrupt Timer (RIT) register structure definition | |
| Real-Time Clock (RTC) register structure definition | |
| System Control (SC) register structure definition | |
| Serial Peripheral Interface (SPI) register structure definition | |
| Synchronous Serial Communication (SSP) register structure definition | |
| Timer (TIM) register structure definition | |
| Universal Asynchronous Receiver Transmitter 0 (UART0) register structure definition | |
| Universal Asynchronous Receiver Transmitter 1 (UART1) register structure definition | |
| Universal Asynchronous Receiver Transmitter (UART) register structure definition | |
| Universal Serial Bus (USB) register structure definition | |
| Watchdog Timer (WDT) register structure definition | |
| MCPWM Capture Configuration type definition | |
| Motor Control PWM Channel Configuration structure type definition | |
| MCPWM Count Control Configuration type definition | |
| NVIC Init Structure definition | |
| Nested Vectored Interrupt Controller (NVIC) register structure definition | |
| Option Bytes Registers | |
| Pin configuration structure | |
| PWM Capture Input configuration structure | |
| Configuration structure in PWM COUNTER mode | |
| PWM Match channel configuration structure | |
| Configuration structure in PWM TIMER mode | |
| Power Control | |
| QEI Configuration structure type definition | |
| Timer Reload Configuration structure type definition | |
| Reset and Clock Control | |
| Time structure definitions for easy manipulate the data | |
| Real-Time Clock | |
| RX Descriptor structure type definition | |
| RX Status structure type definition | |
| System Control Block (SCB) register structure definition | |
| SD host Interface | |
| Standard ID Frame Format Entry structure | |
| Group of Standard ID Frame Format Entry structure | |
| SPI configuration structure | |
| SPI Data configuration structure definitions | |
| SPI Init structure definition | |
| Serial Peripheral Interface | |
| SSP configuration structure | |
| SPI Data configuration structure definitions | |
| System Tick Timer (SysTick) register structure definition | |
| BDTR structure definition | |
| Capture Input configuration structure | |
| Configuration structure in COUNTER mode | |
| TIM Input Capture Init structure definition | |
| Match channel configuration structure | |
| TIM Output Compare Init structure definition | |
| TIM Time Base Init structure definition | |
| Configuration structure in TIMER mode | |
| TIM | |
| TX Descriptor structure type definition | |
| TX Status structure type definition | |
| UART1 Full modem - RS485 Control configuration type | |
| Auto Baudrate mode configuration type definition | |
| UART Configuration Structure definition | |
| UART FIFO Configuration Structure definition | |
| USART Clock Init Structure definition | |
| USART Init Structure definition | |
| Universal Synchronous Asynchronous Receiver Transmitter | |
| Window WATCHDOG | |