lpc17xx_ssp.h

Go to the documentation of this file.

/***********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
#ifndef LPC17XX_SSP_H_
#define LPC17XX_SSP_H_

/* Includes ------------------------------------------------------------------- */
#include "LPC17xx.h"
#include "lpc_types.h"


#ifdef __cplusplus
extern "C"
{
#endif

/* Public Macros -------------------------------------------------------------- */
/*********************************************************************/
#define SSP_CPHA_FIRST          ((uint32_t)(0))
#define SSP_CPHA_SECOND         SSP_CR0_CPHA_SECOND


/* There's no bug here!!!
 * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames.
 * That means the active clock is in HI state.
 * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock
 * high between frames. That means the active clock is in LO state.
 */
#define SSP_CPOL_HI             ((uint32_t)(0))
#define SSP_CPOL_LO             SSP_CR0_CPOL_HI

#define SSP_SLAVE_MODE          SSP_CR1_SLAVE_EN
#define SSP_MASTER_MODE         ((uint32_t)(0))

#define SSP_DATABIT_4       SSP_CR0_DSS(4)          
#define SSP_DATABIT_5       SSP_CR0_DSS(5)          
#define SSP_DATABIT_6       SSP_CR0_DSS(6)          
#define SSP_DATABIT_7       SSP_CR0_DSS(7)          
#define SSP_DATABIT_8       SSP_CR0_DSS(8)          
#define SSP_DATABIT_9       SSP_CR0_DSS(9)          
#define SSP_DATABIT_10      SSP_CR0_DSS(10)         
#define SSP_DATABIT_11      SSP_CR0_DSS(11)         
#define SSP_DATABIT_12      SSP_CR0_DSS(12)         
#define SSP_DATABIT_13      SSP_CR0_DSS(13)         
#define SSP_DATABIT_14      SSP_CR0_DSS(14)         
#define SSP_DATABIT_15      SSP_CR0_DSS(15)         
#define SSP_DATABIT_16      SSP_CR0_DSS(16)         
#define SSP_FRAME_SPI       SSP_CR0_FRF_SPI

#define SSP_FRAME_TI        SSP_CR0_FRF_TI

#define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE

/*********************************************************************/
#define SSP_STAT_TXFIFO_EMPTY       SSP_SR_TFE

#define SSP_STAT_TXFIFO_NOTFULL     SSP_SR_TNF

#define SSP_STAT_RXFIFO_NOTEMPTY    SSP_SR_RNE

#define SSP_STAT_RXFIFO_FULL        SSP_SR_RFF

#define SSP_STAT_BUSY               SSP_SR_BSY

/*********************************************************************/
#define SSP_INTCFG_ROR      SSP_IMSC_ROR

#define SSP_INTCFG_RT       SSP_IMSC_RT

#define SSP_INTCFG_RX       SSP_IMSC_RX

#define SSP_INTCFG_TX       SSP_IMSC_TX

/*********************************************************************/
#define SSP_INTSTAT_ROR     SSP_MIS_ROR

#define SSP_INTSTAT_RT      SSP_MIS_RT

#define SSP_INTSTAT_RX      SSP_MIS_RX

#define SSP_INTSTAT_TX      SSP_MIS_TX

/*********************************************************************/
#define SSP_INTSTAT_RAW_ROR     SSP_RIS_ROR

#define SSP_INTSTAT_RAW_RT      SSP_RIS_RT

#define SSP_INTSTAT_RAW_RX      SSP_RIS_RX

#define SSP_INTSTAT_RAW_TX      SSP_RIS_TX

/*********************************************************************/
#define SSP_INTCLR_ROR      SSP_ICR_ROR

#define SSP_INTCLR_RT       SSP_ICR_RT

/*********************************************************************/
#define SSP_DMA_RX      SSP_DMA_RXDMA_EN

#define SSP_DMA_TX      SSP_DMA_TXDMA_EN

/* SSP Status Implementation definitions */
#define SSP_STAT_DONE       (1UL<<8)        
#define SSP_STAT_ERROR      (1UL<<9)        
/* Private Macros ------------------------------------------------------------- */

/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************/
#define SSP_CR0_DSS(n)          ((uint32_t)((n-1)&0xF))

#define SSP_CR0_FRF_SPI         ((uint32_t)(0<<4))

#define SSP_CR0_FRF_TI          ((uint32_t)(1<<4))

#define SSP_CR0_FRF_MICROWIRE   ((uint32_t)(2<<4))

#define SSP_CR0_CPOL_HI     ((uint32_t)(1<<6))

#define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7))

#define SSP_CR0_SCR(n)      ((uint32_t)((n&0xFF)<<8))

#define SSP_CR0_BITMASK     ((uint32_t)(0xFFFF))

/*********************************************************************/
#define SSP_CR1_LBM_EN      ((uint32_t)(1<<0))

#define SSP_CR1_SSP_EN      ((uint32_t)(1<<1))

#define SSP_CR1_SLAVE_EN    ((uint32_t)(1<<2))

#define SSP_CR1_SO_DISABLE  ((uint32_t)(1<<3))

#define SSP_CR1_BITMASK     ((uint32_t)(0x0F))

/*********************************************************************/
#define SSP_DR_BITMASK(n)   ((n)&0xFFFF)

/*********************************************************************/
#define SSP_SR_TFE      ((uint32_t)(1<<0))

#define SSP_SR_TNF      ((uint32_t)(1<<1))

#define SSP_SR_RNE      ((uint32_t)(1<<2))

#define SSP_SR_RFF      ((uint32_t)(1<<3))

#define SSP_SR_BSY      ((uint32_t)(1<<4))

#define SSP_SR_BITMASK  ((uint32_t)(0x1F))

/*********************************************************************/
#define SSP_CPSR_CPDVSR(n)  ((uint32_t)(n&0xFF))

#define SSP_CPSR_BITMASK    ((uint32_t)(0xFF))

/*********************************************************************/
#define SSP_IMSC_ROR    ((uint32_t)(1<<0))

#define SSP_IMSC_RT     ((uint32_t)(1<<1))

#define SSP_IMSC_RX     ((uint32_t)(1<<2))

#define SSP_IMSC_TX     ((uint32_t)(1<<3))

#define SSP_IMSC_BITMASK    ((uint32_t)(0x0F))

/*********************************************************************/
#define SSP_RIS_ROR     ((uint32_t)(1<<0))

#define SSP_RIS_RT      ((uint32_t)(1<<1))

#define SSP_RIS_RX      ((uint32_t)(1<<2))

#define SSP_RIS_TX      ((uint32_t)(1<<3))

#define SSP_RIS_BITMASK ((uint32_t)(0x0F))

/*********************************************************************/
#define SSP_MIS_ROR     ((uint32_t)(1<<0))

#define SSP_MIS_RT      ((uint32_t)(1<<1))

#define SSP_MIS_RX      ((uint32_t)(1<<2))

#define SSP_MIS_TX      ((uint32_t)(1<<3))

#define SSP_MIS_BITMASK ((uint32_t)(0x0F))

/*********************************************************************/
#define SSP_ICR_ROR     ((uint32_t)(1<<0))

#define SSP_ICR_RT      ((uint32_t)(1<<1))

#define SSP_ICR_BITMASK ((uint32_t)(0x03))

/*********************************************************************/
#define SSP_DMA_RXDMA_EN    ((uint32_t)(1<<0))

#define SSP_DMA_TXDMA_EN    ((uint32_t)(1<<1))

#define SSP_DMA_BITMASK     ((uint32_t)(0x03))


/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
#define PARAM_SSPx(n)   ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \
|| (((uint32_t *)n)==((uint32_t *)LPC_SSP1)))

#define PARAM_SSP_CPHA(n)       ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND))

#define PARAM_SSP_CPOL(n)       ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO))

/* Macro check master/slave mode */
#define PARAM_SSP_MODE(n)       ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE))

/* Macro check databit value */
#define PARAM_SSP_DATABIT(n)    ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \
|| (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \
|| (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \
|| (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \
|| (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \
|| (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \
|| (n==SSP_DATABIT_15))

/* Macro check frame type */
#define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\
|| (n==SSP_FRAME_MICROWIRE))

/* Macro check SSP status */
#define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \
|| (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \
|| (n==SSP_STAT_BUSY))

/* Macro check interrupt configuration */
#define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \
|| (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX))

/* Macro check interrupt status value */
#define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \
|| (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX))

/* Macro check interrupt status raw value */
#define PARAM_SSP_INTSTAT_RAW(n)    ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \
|| (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX))

/* Macro check interrupt clear mode */
#define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT))

/* Macro check DMA mode */
#define PARAM_SSP_DMA(n)    ((n==SSP_DMA_TX) || (n==SSP_DMA_RX))

/* Public Types --------------------------------------------------------------- */
typedef struct {
    uint32_t Databit;       
    uint32_t CPHA;          
    uint32_t CPOL;          
    uint32_t Mode;          
    uint32_t FrameFormat;   
    uint32_t ClockRate;     
} SSP_CFG_Type;

typedef enum {
    SSP_TRANSFER_POLLING = 0,   
    SSP_TRANSFER_INTERRUPT      
} SSP_TRANSFER_Type;

typedef struct {
    void *tx_data;              
    uint32_t tx_cnt;            
    void *rx_data;              
    uint32_t rx_cnt;            
    uint32_t length;            
    uint32_t status;            
} SSP_DATA_SETUP_Type;


/* Public Functions ----------------------------------------------------------- */
/* SSP Init/DeInit functions --------------------------------------------------*/
void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct);
void SSP_DeInit(LPC_SSP_TypeDef* SSPx);

/* SSP configure functions ----------------------------------------------------*/
void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct);

/* SSP enable/disable functions -----------------------------------------------*/
void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState);
void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState);

/* SSP get information functions ----------------------------------------------*/
FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType);
uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx);
IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType);
uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx);
IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType);

/* SSP transfer data functions ------------------------------------------------*/
void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data);
uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx);
int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \
                        SSP_TRANSFER_Type xfType);

/* SSP IRQ function ------------------------------------------------------------*/
void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState);
void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType);


#ifdef __cplusplus
}
#endif

#endif /* LPC17XX_SSP_H_ */

/* --------------------------------- End Of File ------------------------------ */