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| #define | __MPU_PRESENT 1 |
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| #define | __NVIC_PRIO_BITS 5 |
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| #define | __Vendor_SysTickConfig 0 |
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| #define | LPC_FLASH_BASE (0x00000000UL) |
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| #define | LPC_RAM_BASE (0x10000000UL) |
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| #define | LPC_AHBRAM0_BASE (0x2007C000UL) |
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| #define | LPC_AHBRAM1_BASE (0x20080000UL) |
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| #define | LPC_GPIO_BASE (0x2009C000UL) |
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| #define | LPC_APB0_BASE (0x40000000UL) |
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| #define | LPC_APB1_BASE (0x40080000UL) |
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| #define | LPC_AHB_BASE (0x50000000UL) |
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| #define | LPC_CM3_BASE (0xE0000000UL) |
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| #define | LPC_WDT_BASE (LPC_APB0_BASE + 0x00000) |
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| #define | LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000) |
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| #define | LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000) |
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| #define | LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000) |
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| #define | LPC_UART1_BASE (LPC_APB0_BASE + 0x10000) |
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| #define | LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000) |
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| #define | LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000) |
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| #define | LPC_SPI_BASE (LPC_APB0_BASE + 0x20000) |
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| #define | LPC_RTC_BASE (LPC_APB0_BASE + 0x24000) |
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| #define | LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080) |
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| #define | LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000) |
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| #define | LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000) |
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| #define | LPC_ADC_BASE (LPC_APB0_BASE + 0x34000) |
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| #define | LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000) |
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| #define | LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000) |
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| #define | LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000) |
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| #define | LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000) |
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| #define | LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000) |
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| #define | LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000) |
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| #define | LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000) |
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| #define | LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000) |
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| #define | LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000) |
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| #define | LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000) |
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| #define | LPC_UART2_BASE (LPC_APB1_BASE + 0x18000) |
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| #define | LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000) |
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| #define | LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000) |
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| #define | LPC_I2S_BASE (LPC_APB1_BASE + 0x28000) |
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| #define | LPC_RIT_BASE (LPC_APB1_BASE + 0x30000) |
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| #define | LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000) |
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| #define | LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000) |
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| #define | LPC_SC_BASE (LPC_APB1_BASE + 0x7C000) |
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| #define | LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000) |
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| #define | LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000) |
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| #define | LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100) |
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| #define | LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120) |
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| #define | LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140) |
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| #define | LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160) |
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| #define | LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180) |
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| #define | LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0) |
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| #define | LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0) |
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| #define | LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0) |
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| #define | LPC_USB_BASE (LPC_AHB_BASE + 0x0C000) |
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| #define | LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000) |
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| #define | LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020) |
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| #define | LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040) |
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| #define | LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060) |
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| #define | LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080) |
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| #define | LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE ) |
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| #define | LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE ) |
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| #define | LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE ) |
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| #define | LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE ) |
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| #define | LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE ) |
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| #define | LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE ) |
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| #define | LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE ) |
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| #define | LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE ) |
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| #define | LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE ) |
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| #define | LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE ) |
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| #define | LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE ) |
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| #define | LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE ) |
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| #define | LPC_UART0 ((LPC_UART_TypeDef *) LPC_UART0_BASE ) |
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| #define | LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE ) |
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| #define | LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE ) |
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| #define | LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE ) |
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| #define | LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE ) |
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| #define | LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE ) |
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| #define | LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE ) |
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| #define | LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE ) |
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| #define | LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE ) |
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| #define | LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE ) |
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| #define | LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE ) |
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| #define | LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE ) |
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| #define | LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE ) |
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| #define | LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE ) |
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| #define | LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE ) |
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| #define | LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE ) |
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| #define | LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE ) |
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| #define | LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE) |
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| #define | LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE ) |
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| #define | LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE ) |
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| #define | LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE ) |
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| #define | LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE ) |
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| #define | LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE ) |
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| #define | LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE ) |
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| #define | LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE ) |
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| #define | LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE ) |
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| #define | DMAREQSEL (*(__IO uint32_t *) ( 0x4000C1C4)) |
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| #define | LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE ) |
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| #define | LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE ) |
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| #define | LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE ) |
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| #define | LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE ) |
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| #define | LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE ) |
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| #define | LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE ) |
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| #define | LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE ) |
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| #define | LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE ) |
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| #define | LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE ) |
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1.8.4 
