Configuration_section_for_CMSIS

Macros
#define	__MPU_PRESENT   0
	Configuration of the Cortex-M3 Processor and Core Peripherals. More...
#define	__NVIC_PRIO_BITS   4
#define	__Vendor_SysTickConfig   0

Typedefs
typedef enum IRQn	IRQn_Type
	STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section. More...

Enumerations
enum	IRQn {   NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,   SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,   WDT_IRQn = 0, TIMER0_IRQn = 1, TIMER1_IRQn = 2, TIMER2_IRQn = 3,   TIMER3_IRQn = 4, UART0_IRQn = 5, UART1_IRQn = 6, UART2_IRQn = 7,   UART3_IRQn = 8, PWM1_IRQn = 9, I2C0_IRQn = 10, I2C1_IRQn = 11,   I2C2_IRQn = 12, SPI_IRQn = 13, SSP0_IRQn = 14, SSP1_IRQn = 15,   PLL0_IRQn = 16, RTC_IRQn = 17, EINT0_IRQn = 18, EINT1_IRQn = 19,   EINT2_IRQn = 20, EINT3_IRQn = 21, ADC_IRQn = 22, BOD_IRQn = 23,   USB_IRQn = 24, CAN_IRQn = 25, DMA_IRQn = 26, I2S_IRQn = 27,   ENET_IRQn = 28, RIT_IRQn = 29, MCPWM_IRQn = 30, QEI_IRQn = 31,   PLL1_IRQn = 32, USBActivity_IRQn = 33, CANActivity_IRQn = 34, NonMaskableInt_IRQn = -14,   MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5,   DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0,   PVD_IRQn = 1, TAMPER_IRQn = 2, RTC_IRQn = 3, FLASH_IRQn = 4,   RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8,   EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Channel1_IRQn = 11, DMA1_Channel2_IRQn = 12,   DMA1_Channel3_IRQn = 13, DMA1_Channel4_IRQn = 14, DMA1_Channel5_IRQn = 15, DMA1_Channel6_IRQn = 16,   DMA1_Channel7_IRQn = 17 }
	STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section. More...

Detailed Description

Macro Definition Documentation

#define __MPU_PRESENT   0

Configuration of the Cortex-M3 Processor and Core Peripherals.

Other STM32 devices does not provide an MPU

Definition at line 158 of file stm32f10x.h.

#define __NVIC_PRIO_BITS   4

STM32 uses 4 Bits for the Priority Levels

Definition at line 160 of file stm32f10x.h.

#define __Vendor_SysTickConfig   0

Set to 1 if different SysTick Config is used

Definition at line 161 of file stm32f10x.h.

Typedef Documentation

typedef enum IRQn IRQn_Type

STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section.

Enumeration Type Documentation

enum IRQn

STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section.

Enumerator
NonMaskableInt_IRQn	2 Non Maskable Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WDT_IRQn	Watchdog Timer Interrupt
TIMER0_IRQn	Timer0 Interrupt
TIMER1_IRQn	Timer1 Interrupt
TIMER2_IRQn	Timer2 Interrupt
TIMER3_IRQn	Timer3 Interrupt
UART0_IRQn	UART0 Interrupt
UART1_IRQn	UART1 Interrupt
UART2_IRQn	UART2 Interrupt
UART3_IRQn	UART3 Interrupt
PWM1_IRQn	PWM1 Interrupt
I2C0_IRQn	I2C0 Interrupt
I2C1_IRQn	I2C1 Interrupt
I2C2_IRQn	I2C2 Interrupt
SPI_IRQn	SPI Interrupt
SSP0_IRQn	SSP0 Interrupt
SSP1_IRQn	SSP1 Interrupt
PLL0_IRQn	PLL0 Lock (Main PLL) Interrupt
RTC_IRQn	Real Time Clock Interrupt
EINT0_IRQn	External Interrupt 0 Interrupt
EINT1_IRQn	External Interrupt 1 Interrupt
EINT2_IRQn	External Interrupt 2 Interrupt
EINT3_IRQn	External Interrupt 3 Interrupt
ADC_IRQn	A/D Converter Interrupt
BOD_IRQn	Brown-Out Detect Interrupt
USB_IRQn	USB Interrupt
CAN_IRQn	CAN Interrupt
DMA_IRQn	General Purpose DMA Interrupt
I2S_IRQn	I2S Interrupt
ENET_IRQn	Ethernet Interrupt
RIT_IRQn	Repetitive Interrupt Timer Interrupt
MCPWM_IRQn	Motor Control PWM Interrupt
QEI_IRQn	Quadrature Encoder Interface Interrupt
PLL1_IRQn	PLL1 Lock (USB PLL) Interrupt
USBActivity_IRQn	USB Activity Interrupt
CANActivity_IRQn	CAN Activity Interrupt
NonMaskableInt_IRQn	2 Non Maskable Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WWDG_IRQn	Window WatchDog Interrupt
PVD_IRQn	PVD through EXTI Line detection Interrupt
TAMPER_IRQn	Tamper Interrupt
RTC_IRQn	RTC global Interrupt
FLASH_IRQn	FLASH global Interrupt
RCC_IRQn	RCC global Interrupt
EXTI0_IRQn	EXTI Line0 Interrupt
EXTI1_IRQn	EXTI Line1 Interrupt
EXTI2_IRQn	EXTI Line2 Interrupt
EXTI3_IRQn	EXTI Line3 Interrupt
EXTI4_IRQn	EXTI Line4 Interrupt
DMA1_Channel1_IRQn	DMA1 Channel 1 global Interrupt
DMA1_Channel2_IRQn	DMA1 Channel 2 global Interrupt
DMA1_Channel3_IRQn	DMA1 Channel 3 global Interrupt
DMA1_Channel4_IRQn	DMA1 Channel 4 global Interrupt
DMA1_Channel5_IRQn	DMA1 Channel 5 global Interrupt
DMA1_Channel6_IRQn	DMA1 Channel 6 global Interrupt
DMA1_Channel7_IRQn	DMA1 Channel 7 global Interrupt

Definition at line 167 of file stm32f10x.h.