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system_LPC17xx.c
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1 /**************************************************************************/
26 #include <stdint.h>
27 #include "LPC17xx.h"
28 
29 
34 /*
35 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
36 */
37 
38 /*--------------------- Clock Configuration ----------------------------------
39 //
40 // <e> Clock Configuration
41 // <h> System Controls and Status Register (SCS)
42 // <o1.4> OSCRANGE: Main Oscillator Range Select
43 // <0=> 1 MHz to 20 MHz
44 // <1=> 15 MHz to 24 MHz
45 // <e1.5> OSCEN: Main Oscillator Enable
46 // </e>
47 // </h>
48 //
49 // <h> Clock Source Select Register (CLKSRCSEL)
50 // <o2.0..1> CLKSRC: PLL Clock Source Selection
51 // <0=> Internal RC oscillator
52 // <1=> Main oscillator
53 // <2=> RTC oscillator
54 // </h>
55 //
56 // <e3> PLL0 Configuration (Main PLL)
57 // <h> PLL0 Configuration Register (PLL0CFG)
58 // <i> F_cco0 = (2 * M * F_in) / N
59 // <i> F_in must be in the range of 32 kHz to 50 MHz
60 // <i> F_cco0 must be in the range of 275 MHz to 550 MHz
61 // <o4.0..14> MSEL: PLL Multiplier Selection
62 // <6-32768><#-1>
63 // <i> M Value
64 // <o4.16..23> NSEL: PLL Divider Selection
65 // <1-256><#-1>
66 // <i> N Value
67 // </h>
68 // </e>
69 //
70 // <e5> PLL1 Configuration (USB PLL)
71 // <h> PLL1 Configuration Register (PLL1CFG)
72 // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P)
73 // <i> F_cco1 = F_osc * M * 2 * P
74 // <i> F_cco1 must be in the range of 156 MHz to 320 MHz
75 // <o6.0..4> MSEL: PLL Multiplier Selection
76 // <1-32><#-1>
77 // <i> M Value (for USB maximum value is 4)
78 // <o6.5..6> PSEL: PLL Divider Selection
79 // <0=> 1
80 // <1=> 2
81 // <2=> 4
82 // <3=> 8
83 // <i> P Value
84 // </h>
85 // </e>
86 //
87 // <h> CPU Clock Configuration Register (CCLKCFG)
88 // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0
89 // <3-256><#-1>
90 // </h>
91 //
92 // <h> USB Clock Configuration Register (USBCLKCFG)
93 // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL0
94 // <0-15>
95 // <i> Divide is USBSEL + 1
96 // </h>
97 //
98 // <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
99 // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT
100 // <0=> Pclk = Cclk / 4
101 // <1=> Pclk = Cclk
102 // <2=> Pclk = Cclk / 2
103 // <3=> Pclk = Hclk / 8
104 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0
105 // <0=> Pclk = Cclk / 4
106 // <1=> Pclk = Cclk
107 // <2=> Pclk = Cclk / 2
108 // <3=> Pclk = Hclk / 8
109 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1
110 // <0=> Pclk = Cclk / 4
111 // <1=> Pclk = Cclk
112 // <2=> Pclk = Cclk / 2
113 // <3=> Pclk = Hclk / 8
114 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0
115 // <0=> Pclk = Cclk / 4
116 // <1=> Pclk = Cclk
117 // <2=> Pclk = Cclk / 2
118 // <3=> Pclk = Hclk / 8
119 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1
120 // <0=> Pclk = Cclk / 4
121 // <1=> Pclk = Cclk
122 // <2=> Pclk = Cclk / 2
123 // <3=> Pclk = Hclk / 8
124 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1
125 // <0=> Pclk = Cclk / 4
126 // <1=> Pclk = Cclk
127 // <2=> Pclk = Cclk / 2
128 // <3=> Pclk = Hclk / 8
129 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0
130 // <0=> Pclk = Cclk / 4
131 // <1=> Pclk = Cclk
132 // <2=> Pclk = Cclk / 2
133 // <3=> Pclk = Hclk / 8
134 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI
135 // <0=> Pclk = Cclk / 4
136 // <1=> Pclk = Cclk
137 // <2=> Pclk = Cclk / 2
138 // <3=> Pclk = Hclk / 8
139 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1
140 // <0=> Pclk = Cclk / 4
141 // <1=> Pclk = Cclk
142 // <2=> Pclk = Cclk / 2
143 // <3=> Pclk = Hclk / 8
144 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC
145 // <0=> Pclk = Cclk / 4
146 // <1=> Pclk = Cclk
147 // <2=> Pclk = Cclk / 2
148 // <3=> Pclk = Hclk / 8
149 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC
150 // <0=> Pclk = Cclk / 4
151 // <1=> Pclk = Cclk
152 // <2=> Pclk = Cclk / 2
153 // <3=> Pclk = Hclk / 8
154 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1
155 // <0=> Pclk = Cclk / 4
156 // <1=> Pclk = Cclk
157 // <2=> Pclk = Cclk / 2
158 // <3=> Pclk = Hclk / 6
159 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2
160 // <0=> Pclk = Cclk / 4
161 // <1=> Pclk = Cclk
162 // <2=> Pclk = Cclk / 2
163 // <3=> Pclk = Hclk / 6
164 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF
165 // <0=> Pclk = Cclk / 4
166 // <1=> Pclk = Cclk
167 // <2=> Pclk = Cclk / 2
168 // <3=> Pclk = Hclk / 6
169 // </h>
170 //
171 // <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
172 // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface
173 // <0=> Pclk = Cclk / 4
174 // <1=> Pclk = Cclk
175 // <2=> Pclk = Cclk / 2
176 // <3=> Pclk = Hclk / 8
177 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs
178 // <0=> Pclk = Cclk / 4
179 // <1=> Pclk = Cclk
180 // <2=> Pclk = Cclk / 2
181 // <3=> Pclk = Hclk / 8
182 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block
183 // <0=> Pclk = Cclk / 4
184 // <1=> Pclk = Cclk
185 // <2=> Pclk = Cclk / 2
186 // <3=> Pclk = Hclk / 8
187 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1
188 // <0=> Pclk = Cclk / 4
189 // <1=> Pclk = Cclk
190 // <2=> Pclk = Cclk / 2
191 // <3=> Pclk = Hclk / 8
192 // <o10.10..11> PCLK_SSP0: Peripheral Clock Selection for SSP0
193 // <0=> Pclk = Cclk / 4
194 // <1=> Pclk = Cclk
195 // <2=> Pclk = Cclk / 2
196 // <3=> Pclk = Hclk / 8
197 // <o10.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
198 // <0=> Pclk = Cclk / 4
199 // <1=> Pclk = Cclk
200 // <2=> Pclk = Cclk / 2
201 // <3=> Pclk = Hclk / 8
202 // <o10.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
203 // <0=> Pclk = Cclk / 4
204 // <1=> Pclk = Cclk
205 // <2=> Pclk = Cclk / 2
206 // <3=> Pclk = Hclk / 8
207 // <o10.16..17> PCLK_UART2: Peripheral Clock Selection for UART2
208 // <0=> Pclk = Cclk / 4
209 // <1=> Pclk = Cclk
210 // <2=> Pclk = Cclk / 2
211 // <3=> Pclk = Hclk / 8
212 // <o10.18..19> PCLK_UART3: Peripheral Clock Selection for UART3
213 // <0=> Pclk = Cclk / 4
214 // <1=> Pclk = Cclk
215 // <2=> Pclk = Cclk / 2
216 // <3=> Pclk = Hclk / 8
217 // <o10.20..21> PCLK_I2C2: Peripheral Clock Selection for I2C2
218 // <0=> Pclk = Cclk / 4
219 // <1=> Pclk = Cclk
220 // <2=> Pclk = Cclk / 2
221 // <3=> Pclk = Hclk / 8
222 // <o10.22..23> PCLK_I2S: Peripheral Clock Selection for I2S
223 // <0=> Pclk = Cclk / 4
224 // <1=> Pclk = Cclk
225 // <2=> Pclk = Cclk / 2
226 // <3=> Pclk = Hclk / 8
227 // <o10.26..27> PCLK_RIT: Peripheral Clock Selection for the Repetitive Interrupt Timer
228 // <0=> Pclk = Cclk / 4
229 // <1=> Pclk = Cclk
230 // <2=> Pclk = Cclk / 2
231 // <3=> Pclk = Hclk / 8
232 // <o10.28..29> PCLK_SYSCON: Peripheral Clock Selection for the System Control Block
233 // <0=> Pclk = Cclk / 4
234 // <1=> Pclk = Cclk
235 // <2=> Pclk = Cclk / 2
236 // <3=> Pclk = Hclk / 8
237 // <o10.30..31> PCLK_MC: Peripheral Clock Selection for the Motor Control PWM
238 // <0=> Pclk = Cclk / 4
239 // <1=> Pclk = Cclk
240 // <2=> Pclk = Cclk / 2
241 // <3=> Pclk = Hclk / 8
242 // </h>
243 //
244 // <h> Power Control for Peripherals Register (PCONP)
245 // <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
246 // <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
247 // <o11.3> PCUART0: UART 0 power/clock enable
248 // <o11.4> PCUART1: UART 1 power/clock enable
249 // <o11.6> PCPWM1: PWM 1 power/clock enable
250 // <o11.7> PCI2C0: I2C interface 0 power/clock enable
251 // <o11.8> PCSPI: SPI interface power/clock enable
252 // <o11.9> PCRTC: RTC power/clock enable
253 // <o11.10> PCSSP1: SSP interface 1 power/clock enable
254 // <o11.12> PCAD: A/D converter power/clock enable
255 // <o11.13> PCCAN1: CAN controller 1 power/clock enable
256 // <o11.14> PCCAN2: CAN controller 2 power/clock enable
257 // <o11.15> PCGPIO: GPIOs power/clock enable
258 // <o11.16> PCRIT: Repetitive interrupt timer power/clock enable
259 // <o11.17> PCMC: Motor control PWM power/clock enable
260 // <o11.18> PCQEI: Quadrature encoder interface power/clock enable
261 // <o11.19> PCI2C1: I2C interface 1 power/clock enable
262 // <o11.21> PCSSP0: SSP interface 0 power/clock enable
263 // <o11.22> PCTIM2: Timer 2 power/clock enable
264 // <o11.23> PCTIM3: Timer 3 power/clock enable
265 // <o11.24> PCUART2: UART 2 power/clock enable
266 // <o11.25> PCUART3: UART 3 power/clock enable
267 // <o11.26> PCI2C2: I2C interface 2 power/clock enable
268 // <o11.27> PCI2S: I2S interface power/clock enable
269 // <o11.29> PCGPDMA: GP DMA function power/clock enable
270 // <o11.30> PCENET: Ethernet block power/clock enable
271 // <o11.31> PCUSB: USB interface power/clock enable
272 // </h>
273 //
274 // <h> Clock Output Configuration Register (CLKOUTCFG)
275 // <o12.0..3> CLKOUTSEL: Selects clock source for CLKOUT
276 // <0=> CPU clock
277 // <1=> Main oscillator
278 // <2=> Internal RC oscillator
279 // <3=> USB clock
280 // <4=> RTC oscillator
281 // <o12.4..7> CLKOUTDIV: Selects clock divider for CLKOUT
282 // <1-16><#-1>
283 // <o12.8> CLKOUT_EN: CLKOUT enable control
284 // </h>
285 //
286 // </e>
287 */
288 
289 
290 
295 #define CLOCK_SETUP 1
296 #define SCS_Val 0x00000020
297 #define CLKSRCSEL_Val 0x00000001
298 #define PLL0_SETUP 1
299 #define PLL0CFG_Val 0x00050063
300 #define PLL1_SETUP 1
301 #define PLL1CFG_Val 0x00000023
302 #define CCLKCFG_Val 0x00000003
303 #define USBCLKCFG_Val 0x00000000
304 #define PCLKSEL0_Val 0x00000000
305 #define PCLKSEL1_Val 0x00000000
306 #define PCONP_Val 0x042887DE
307 #define CLKOUTCFG_Val 0x00000000
308 
309 
310 /*--------------------- Flash Accelerator Configuration ----------------------
311 //
312 // <e> Flash Accelerator Configuration
313 // <o1.0..11> Reserved
314 // <o1.12..15> FLASHTIM: Flash Access Time
315 // <0=> 1 CPU clock (for CPU clock up to 20 MHz)
316 // <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
317 // <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
318 // <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
319 // <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
320 // <5=> 6 CPU clocks (for any CPU clock)
321 // </e>
322 */
323 #define FLASH_SETUP 1
324 #define FLASHCFG_Val 0x0000303A
325 
326 /*
327 //-------- <<< end of configuration section >>> ------------------------------
328 */
329 
330 /*----------------------------------------------------------------------------
331  Check the register settings
332  *----------------------------------------------------------------------------*/
333 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
334 #define CHECK_RSVD(val, mask) (val & mask)
335 
336 /* Clock Configuration -------------------------------------------------------*/
337 #if (CHECK_RSVD((SCS_Val), ~0x00000030))
338  #error "SCS: Invalid values of reserved bits!"
339 #endif
340 
341 #if (CHECK_RANGE((CLKSRCSEL_Val), 0, 2))
342  #error "CLKSRCSEL: Value out of range!"
343 #endif
344 
345 #if (CHECK_RSVD((PLL0CFG_Val), ~0x00FF7FFF))
346  #error "PLL0CFG: Invalid values of reserved bits!"
347 #endif
348 
349 #if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
350  #error "PLL1CFG: Invalid values of reserved bits!"
351 #endif
352 
353 #if ((CCLKCFG_Val != 0) && (((CCLKCFG_Val - 1) % 2)))
354  #error "CCLKCFG: CCLKSEL field does not contain only odd values or 0!"
355 #endif
356 
357 #if (CHECK_RSVD((USBCLKCFG_Val), ~0x0000000F))
358  #error "USBCLKCFG: Invalid values of reserved bits!"
359 #endif
360 
361 #if (CHECK_RSVD((PCLKSEL0_Val), 0x000C0C00))
362  #error "PCLKSEL0: Invalid values of reserved bits!"
363 #endif
364 
365 #if (CHECK_RSVD((PCLKSEL1_Val), 0x03000300))
366  #error "PCLKSEL1: Invalid values of reserved bits!"
367 #endif
368 
369 #if (CHECK_RSVD((PCONP_Val), 0x10100821))
370  #error "PCONP: Invalid values of reserved bits!"
371 #endif
372 
373 #if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
374  #error "CLKOUTCFG: Invalid values of reserved bits!"
375 #endif
376 
377 /* Flash Accelerator Configuration -------------------------------------------*/
378 #if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F07F))
379  #error "FLASHCFG: Invalid values of reserved bits!"
380 #endif
381 
382 
383 /*----------------------------------------------------------------------------
384  DEFINES
385  *----------------------------------------------------------------------------*/
386 
387 /*----------------------------------------------------------------------------
388  Define clocks
389  *----------------------------------------------------------------------------*/
390 #define XTAL (12000000UL) /* Oscillator frequency */
391 #define OSC_CLK ( XTAL) /* Main oscillator frequency */
392 #define RTC_CLK ( 32768UL) /* RTC oscillator frequency */
393 #define IRC_OSC ( 4000000UL) /* Internal RC oscillator frequency */
394 
395 
396 /* F_cco0 = (2 * M * F_in) / N */
397 #define __M (((PLL0CFG_Val ) & 0x7FFF) + 1)
398 #define __N (((PLL0CFG_Val >> 16) & 0x00FF) + 1)
399 #define __FCCO(__F_IN) ((2 * __M * __F_IN) / __N)
400 #define __CCLK_DIV (((CCLKCFG_Val ) & 0x00FF) + 1)
401 
402 /* Determine core clock frequency according to settings */
403  #if (PLL0_SETUP)
404  #if ((CLKSRCSEL_Val & 0x03) == 1)
405  #define __CORE_CLK (__FCCO(OSC_CLK) / __CCLK_DIV)
406  #elif ((CLKSRCSEL_Val & 0x03) == 2)
407  #define __CORE_CLK (__FCCO(RTC_CLK) / __CCLK_DIV)
408  #else
409  #define __CORE_CLK (__FCCO(IRC_OSC) / __CCLK_DIV)
410  #endif
411  #else
412  #if ((CLKSRCSEL_Val & 0x03) == 1)
413  #define __CORE_CLK (OSC_CLK / __CCLK_DIV)
414  #elif ((CLKSRCSEL_Val & 0x03) == 2)
415  #define __CORE_CLK (RTC_CLK / __CCLK_DIV)
416  #else
417  #define __CORE_CLK (IRC_OSC / __CCLK_DIV)
418  #endif
419  #endif
420 
429 /*----------------------------------------------------------------------------
430  Clock Variable definitions
431  *----------------------------------------------------------------------------*/
443 /*----------------------------------------------------------------------------
444  Clock functions
445  *----------------------------------------------------------------------------*/
446 
447 
448 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
449 {
450  /* Determine clock frequency according to clock register values */
451  if (((LPC_SC->PLL0STAT >> 24) & 3) == 3) { /* If PLL0 enabled and connected */
452  switch (LPC_SC->CLKSRCSEL & 0x03) {
453  case 0: /* Int. RC oscillator => PLL0 */
454  case 3: /* Reserved, default to Int. RC */
456  ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
457  (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
458  ((LPC_SC->CCLKCFG & 0xFF)+ 1));
459  break;
460  case 1: /* Main oscillator => PLL0 */
462  ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
463  (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
464  ((LPC_SC->CCLKCFG & 0xFF)+ 1));
465  break;
466  case 2: /* RTC oscillator => PLL0 */
468  ((2 * ((LPC_SC->PLL0STAT & 0x7FFF) + 1))) /
469  (((LPC_SC->PLL0STAT >> 16) & 0xFF) + 1) /
470  ((LPC_SC->CCLKCFG & 0xFF)+ 1));
471  break;
472  }
473  } else {
474  switch (LPC_SC->CLKSRCSEL & 0x03) {
475  case 0: /* Int. RC oscillator => PLL0 */
476  case 3: /* Reserved, default to Int. RC */
477  SystemCoreClock = IRC_OSC / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
478  break;
479  case 1: /* Main oscillator => PLL0 */
480  SystemCoreClock = OSC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
481  break;
482  case 2: /* RTC oscillator => PLL0 */
483  SystemCoreClock = RTC_CLK / ((LPC_SC->CCLKCFG & 0xFF)+ 1);
484  break;
485  }
486  }
487 
488 }
489 
499 void SystemInit (void)
500 {
501 #if (CLOCK_SETUP) /* Clock Setup */
502  LPC_SC->SCS = SCS_Val;
503  if (LPC_SC->SCS & (1 << 5)) { /* If Main Oscillator is enabled */
504  while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
505  }
506 
507  LPC_SC->CCLKCFG = CCLKCFG_Val; /* Setup Clock Divider */
508  /* Periphral clock must be selected before PLL0 enabling and connecting
509  * - according errata.lpc1768-16.March.2010 -
510  */
511  LPC_SC->PCLKSEL0 = PCLKSEL0_Val; /* Peripheral Clock Selection */
512  LPC_SC->PCLKSEL1 = PCLKSEL1_Val;
513 
514 #if (PLL0_SETUP)
515  LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for PLL0 */
516 
517  LPC_SC->PLL0CFG = PLL0CFG_Val; /* configure PLL0 */
518  LPC_SC->PLL0FEED = 0xAA;
519  LPC_SC->PLL0FEED = 0x55;
520 
521  LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
522  LPC_SC->PLL0FEED = 0xAA;
523  LPC_SC->PLL0FEED = 0x55;
524  while (!(LPC_SC->PLL0STAT & (1<<26)));/* Wait for PLOCK0 */
525 
526  LPC_SC->PLL0CON = 0x03; /* PLL0 Enable & Connect */
527  LPC_SC->PLL0FEED = 0xAA;
528  LPC_SC->PLL0FEED = 0x55;
529  while (!(LPC_SC->PLL0STAT & ((1<<25) | (1<<24))));/* Wait for PLLC0_STAT & PLLE0_STAT */
530 #endif
531 
532 #if (PLL1_SETUP)
533  LPC_SC->PLL1CFG = PLL1CFG_Val;
534  LPC_SC->PLL1FEED = 0xAA;
535  LPC_SC->PLL1FEED = 0x55;
536 
537  LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
538  LPC_SC->PLL1FEED = 0xAA;
539  LPC_SC->PLL1FEED = 0x55;
540  while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
541 
542  LPC_SC->PLL1CON = 0x03; /* PLL1 Enable & Connect */
543  LPC_SC->PLL1FEED = 0xAA;
544  LPC_SC->PLL1FEED = 0x55;
545  while (!(LPC_SC->PLL1STAT & ((1<< 9) | (1<< 8))));/* Wait for PLLC1_STAT & PLLE1_STAT */
546 #else
547  LPC_SC->USBCLKCFG = USBCLKCFG_Val; /* Setup USB Clock Divider */
548 #endif
549  LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
550 
551  LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
552 #endif
553 
554 #if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
555  LPC_SC->FLASHCFG = FLASHCFG_Val;
556 #endif
557 
558 // Set Vector table offset value
559 #if (__RAM_MODE__==1)
560  SCB->VTOR = 0x10000000 & 0x3FFFFF80;
561 #else
562  SCB->VTOR = 0x00000000 & 0x3FFFFF80;
563 #endif
564 }
565