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lpc17xx_i2s.h
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1 /***********************************************************************/
21 /* Peripheral group ----------------------------------------------------------- */
27 #ifndef LPC17XX_I2S_H_
28 #define LPC17XX_I2S_H_
29 
30 /* Includes ------------------------------------------------------------------- */
31 #include "LPC17xx.h"
32 #include "lpc_types.h"
33 
34 
35 #ifdef __cplusplus
36 extern "C"
37 {
38 #endif
39 
40 /* Public Macros -------------------------------------------------------------- */
45 /*********************************************************************/
49 #define I2S_WORDWIDTH_8 ((uint32_t)(0))
50 #define I2S_WORDWIDTH_16 ((uint32_t)(1))
51 #define I2S_WORDWIDTH_32 ((uint32_t)(3))
52 
53 #define I2S_STEREO ((uint32_t)(0))
54 #define I2S_MONO ((uint32_t)(1))
55 
56 #define I2S_MASTER_MODE ((uint8_t)(0))
57 #define I2S_SLAVE_MODE ((uint8_t)(1))
58 
59 #define I2S_STOP_ENABLE ((uint8_t)(1))
60 #define I2S_STOP_DISABLE ((uint8_t)(0))
61 
62 #define I2S_RESET_ENABLE ((uint8_t)(1))
63 #define I2S_RESET_DISABLE ((uint8_t)(0))
64 
65 #define I2S_MUTE_ENABLE ((uint8_t)(1))
66 #define I2S_MUTE_DISABLE ((uint8_t)(0))
67 
68 #define I2S_TX_MODE ((uint8_t)(0))
69 #define I2S_RX_MODE ((uint8_t)(1))
70 
71 #define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
72 #define I2S_CLKSEL_MCLK ((uint8_t)(2))
73 
74 #define I2S_4PIN_ENABLE ((uint8_t)(1))
75 #define I2S_4PIN_DISABLE ((uint8_t)(0))
76 
77 #define I2S_MCLK_ENABLE ((uint8_t)(1))
78 #define I2S_MCLK_DISABLE ((uint8_t)(0))
79 
80 #define I2S_DMA_1 ((uint8_t)(0))
81 #define I2S_DMA_2 ((uint8_t)(1))
82 
87 /* Private Macros ------------------------------------------------------------- */
92 /*********************************************************************/
96 #define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0))
97 #define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1))
98 #define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3))
100 #define I2S_DAO_MONO ((uint32_t)(1<<2))
101 
102 #define I2S_DAO_STOP ((uint32_t)(1<<3))
103 
104 #define I2S_DAO_RESET ((uint32_t)(1<<4))
105 
106 #define I2S_DAO_SLAVE ((uint32_t)(1<<5))
107 
108 #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
109 
110 #define I2S_DAO_MUTE ((uint32_t)(1<<15))
111 
112 /*********************************************************************/
116 #define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0))
117 #define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1))
118 #define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3))
120 #define I2S_DAI_MONO ((uint32_t)(1<<2))
121 
122 #define I2S_DAI_STOP ((uint32_t)(1<<3))
123 
124 #define I2S_DAI_RESET ((uint32_t)(1<<4))
125 
126 #define I2S_DAI_SLAVE ((uint32_t)(1<<5))
127 
128 #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
129 
130 #define I2S_DAI_MUTE ((uint32_t)(1<<15))
131 
132 /*********************************************************************/
136 #define I2S_STATE_IRQ ((uint32_t)(1))
137 
138 #define I2S_STATE_DMA1 ((uint32_t)(1<<1))
139 
140 #define I2S_STATE_DMA2 ((uint32_t)(1<<2))
141 
142 #define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
143 
144 #define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
145 
146 /*********************************************************************/
150 #define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
151 
152 #define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
153 
154 #define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
155 
156 #define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
157 
158 /*********************************************************************/
162 #define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
163 
164 #define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
165 
166 #define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
167 
168 #define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
169 
170 /*********************************************************************/
174 #define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
175 
176 #define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
177 
178 #define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
179 
180 #define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
181 
182 /********************************************************************************/
186 #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
187 
188 #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
189 
190 #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
191 
192 #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
193 
194 /*************************************************************************************/
197 #define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
198 #define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
199 
200 /**********************************************************************************/
204 #define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
205 
206 #define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
207 
208 #define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
209 
210 #define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
211 
212 #define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
213 
214 #define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
215 
216 
217 /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
219 #define PARAM_I2Sx(n) (((uint32_t *)n)==((uint32_t *)LPC_I2S))
220 
221 #define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000))
222 /* Macro check I2S word width type */
223 #define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
224 ||(n==I2S_WORDWIDTH_32))
225 /* Macro check I2S channel type */
226 #define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO))
227 /* Macro check I2S master/slave mode */
228 #define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
229 /* Macro check I2S stop mode */
230 #define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
231 /* Macro check I2S reset mode */
232 #define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
233 /* Macro check I2S reset mode */
234 #define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
235 /* Macro check I2S transmit/receive mode */
236 #define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
237 /* Macro check I2S clock select mode */
238 #define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
239 /* Macro check I2S 4-pin mode */
240 #define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
241 /* Macro check I2S MCLK mode */
242 #define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
243 /* Macro check I2S DMA mode */
244 #define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2))
245 /* Macro check I2S DMA depth value */
246 #define PARAM_I2S_DMA_DEPTH(n) ((n>=0)||(n<=31))
247 /* Macro check I2S irq level value */
248 #define PARAM_I2S_IRQ_LEVEL(n) ((n>=0)||(n<=31))
249 /* Macro check I2S half-period value */
250 #define PARAM_I2S_HALFPERIOD(n) ((n>0)&&(n<512))
251 /* Macro check I2S bit-rate value */
252 #define PARAM_I2S_BITRATE(n) ((n>=0)&&(n<=63))
253 
259 /* Public Types --------------------------------------------------------------- */
267 typedef struct {
268  uint8_t wordwidth;
272  uint8_t mono;
275  uint8_t stop;
278  uint8_t reset;
281  uint8_t ws_sel;
284  uint8_t mute;
287  uint8_t Reserved0[2];
288 } I2S_CFG_Type;
289 
293 typedef struct {
294  uint8_t DMAIndex;
297  uint8_t depth;
298  uint8_t Reserved0[2];
300 
304 typedef struct{
305  uint8_t clksel;
308  uint8_t fpin;
311  uint8_t mcena;
314  uint8_t Reserved;
316 
317 
323 /* Public Functions ----------------------------------------------------------- */
327 /* I2S Init/DeInit functions ---------*/
328 void I2S_Init(LPC_I2S_TypeDef *I2Sx);
329 void I2S_DeInit(LPC_I2S_TypeDef *I2Sx);
330 
331 /* I2S configuration functions --------*/
332 void I2S_Config(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, I2S_CFG_Type* ConfigStruct);
333 Status I2S_FreqConfig(LPC_I2S_TypeDef *I2Sx, uint32_t Freq, uint8_t TRMode);
334 void I2S_SetBitRate(LPC_I2S_TypeDef *I2Sx, uint8_t bitrate, uint8_t TRMode);
335 void I2S_ModeConfig(LPC_I2S_TypeDef *I2Sx, I2S_MODEConf_Type* ModeConfig, uint8_t TRMode);
336 uint8_t I2S_GetLevel(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
337 
338 /* I2S operate functions -------------*/
339 void I2S_Send(LPC_I2S_TypeDef *I2Sx, uint32_t BufferData);
340 uint32_t I2S_Receive(LPC_I2S_TypeDef* I2Sx);
341 void I2S_Start(LPC_I2S_TypeDef *I2Sx);
342 void I2S_Pause(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
343 void I2S_Mute(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
344 void I2S_Stop(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode);
345 
346 /* I2S DMA functions ----------------*/
347 void I2S_DMAConfig(LPC_I2S_TypeDef *I2Sx, I2S_DMAConf_Type* DMAConfig, uint8_t TRMode);
348 void I2S_DMACmd(LPC_I2S_TypeDef *I2Sx, uint8_t DMAIndex,uint8_t TRMode, FunctionalState NewState);
349 
350 /* I2S IRQ functions ----------------*/
351 void I2S_IRQCmd(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode, FunctionalState NewState);
352 void I2S_IRQConfig(LPC_I2S_TypeDef *I2Sx, uint8_t TRMode, uint8_t level);
353 FunctionalState I2S_GetIRQStatus(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
354 uint8_t I2S_GetIRQDepth(LPC_I2S_TypeDef *I2Sx,uint8_t TRMode);
355 
361 #ifdef __cplusplus
362 }
363 #endif
364 
365 
366 #endif /* LPC17XX_SSP_H_ */
367 
372 /* --------------------------------- End Of File ------------------------------ */