27 #ifndef LPC17XX_I2S_H_
28 #define LPC17XX_I2S_H_
49 #define I2S_WORDWIDTH_8 ((uint32_t)(0))
50 #define I2S_WORDWIDTH_16 ((uint32_t)(1))
51 #define I2S_WORDWIDTH_32 ((uint32_t)(3))
53 #define I2S_STEREO ((uint32_t)(0))
54 #define I2S_MONO ((uint32_t)(1))
56 #define I2S_MASTER_MODE ((uint8_t)(0))
57 #define I2S_SLAVE_MODE ((uint8_t)(1))
59 #define I2S_STOP_ENABLE ((uint8_t)(1))
60 #define I2S_STOP_DISABLE ((uint8_t)(0))
62 #define I2S_RESET_ENABLE ((uint8_t)(1))
63 #define I2S_RESET_DISABLE ((uint8_t)(0))
65 #define I2S_MUTE_ENABLE ((uint8_t)(1))
66 #define I2S_MUTE_DISABLE ((uint8_t)(0))
68 #define I2S_TX_MODE ((uint8_t)(0))
69 #define I2S_RX_MODE ((uint8_t)(1))
71 #define I2S_CLKSEL_FRDCLK ((uint8_t)(0))
72 #define I2S_CLKSEL_MCLK ((uint8_t)(2))
74 #define I2S_4PIN_ENABLE ((uint8_t)(1))
75 #define I2S_4PIN_DISABLE ((uint8_t)(0))
77 #define I2S_MCLK_ENABLE ((uint8_t)(1))
78 #define I2S_MCLK_DISABLE ((uint8_t)(0))
80 #define I2S_DMA_1 ((uint8_t)(0))
81 #define I2S_DMA_2 ((uint8_t)(1))
96 #define I2S_DAO_WORDWIDTH_8 ((uint32_t)(0))
97 #define I2S_DAO_WORDWIDTH_16 ((uint32_t)(1))
98 #define I2S_DAO_WORDWIDTH_32 ((uint32_t)(3))
100 #define I2S_DAO_MONO ((uint32_t)(1<<2))
102 #define I2S_DAO_STOP ((uint32_t)(1<<3))
104 #define I2S_DAO_RESET ((uint32_t)(1<<4))
106 #define I2S_DAO_SLAVE ((uint32_t)(1<<5))
108 #define I2S_DAO_WS_HALFPERIOD(n) ((uint32_t)(n<<6))
110 #define I2S_DAO_MUTE ((uint32_t)(1<<15))
116 #define I2S_DAI_WORDWIDTH_8 ((uint32_t)(0))
117 #define I2S_DAI_WORDWIDTH_16 ((uint32_t)(1))
118 #define I2S_DAI_WORDWIDTH_32 ((uint32_t)(3))
120 #define I2S_DAI_MONO ((uint32_t)(1<<2))
122 #define I2S_DAI_STOP ((uint32_t)(1<<3))
124 #define I2S_DAI_RESET ((uint32_t)(1<<4))
126 #define I2S_DAI_SLAVE ((uint32_t)(1<<5))
128 #define I2S_DAI_WS_HALFPERIOD(n) ((uint32_t)((n&0x1FF)<<6))
130 #define I2S_DAI_MUTE ((uint32_t)(1<<15))
136 #define I2S_STATE_IRQ ((uint32_t)(1))
138 #define I2S_STATE_DMA1 ((uint32_t)(1<<1))
140 #define I2S_STATE_DMA2 ((uint32_t)(1<<2))
142 #define I2S_STATE_RX_LEVEL(n) ((uint32_t)((n&1F)<<8))
144 #define I2S_STATE_TX_LEVEL(n) ((uint32_t)((n&1F)<<16))
150 #define I2S_DMA1_RX_ENABLE ((uint32_t)(1))
152 #define I2S_DMA1_TX_ENABLE ((uint32_t)(1<<1))
154 #define I2S_DMA1_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
156 #define I2S_DMA1_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
162 #define I2S_DMA2_RX_ENABLE ((uint32_t)(1))
164 #define I2S_DMA2_TX_ENABLE ((uint32_t)(1<<1))
166 #define I2S_DMA2_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
168 #define I2S_DMA2_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
174 #define I2S_IRQ_RX_ENABLE ((uint32_t)(1))
176 #define I2S_IRQ_TX_ENABLE ((uint32_t)(1<<1))
178 #define I2S_IRQ_RX_DEPTH(n) ((uint32_t)((n&0x1F)<<8))
180 #define I2S_IRQ_TX_DEPTH(n) ((uint32_t)((n&0x1F)<<16))
186 #define I2S_TXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
188 #define I2S_TXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
190 #define I2S_RXRATE_Y_DIVIDER(n) ((uint32_t)(n&0xFF))
192 #define I2S_RXRATE_X_DIVIDER(n) ((uint32_t)((n&0xFF)<<8))
197 #define I2S_TXBITRATE(n) ((uint32_t)(n&0x3F))
198 #define I2S_RXBITRATE(n) ((uint32_t)(n&0x3F))
204 #define I2S_TXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
206 #define I2S_TXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
208 #define I2S_TXMODE_MCENA ((uint32_t)(1<<3))
210 #define I2S_RXMODE_CLKSEL(n) ((uint32_t)(n&0x03))
212 #define I2S_RXMODE_4PIN_ENABLE ((uint32_t)(1<<2))
214 #define I2S_RXMODE_MCENA ((uint32_t)(1<<3))
219 #define PARAM_I2Sx(n) (((uint32_t *)n)==((uint32_t *)LPC_I2S))
221 #define PRAM_I2S_FREQ(freq) ((freq>=16000)&&(freq <= 96000))
223 #define PARAM_I2S_WORDWIDTH(n) ((n==I2S_WORDWIDTH_8)||(n==I2S_WORDWIDTH_16)\
224 ||(n==I2S_WORDWIDTH_32))
226 #define PARAM_I2S_CHANNEL(n) ((n==I2S_STEREO)||(n==I2S_MONO))
228 #define PARAM_I2S_WS_SEL(n) ((n==I2S_MASTER_MODE)||(n==I2S_SLAVE_MODE))
230 #define PARAM_I2S_STOP(n) ((n==I2S_STOP_ENABLE)||(n==I2S_STOP_DISABLE))
232 #define PARAM_I2S_RESET(n) ((n==I2S_RESET_ENABLE)||(n==I2S_RESET_DISABLE))
234 #define PARAM_I2S_MUTE(n) ((n==I2S_MUTE_ENABLE)||(n==I2S_MUTE_DISABLE))
236 #define PARAM_I2S_TRX(n) ((n==I2S_TX_MODE)||(n==I2S_RX_MODE))
238 #define PARAM_I2S_CLKSEL(n) ((n==I2S_CLKSEL_FRDCLK)||(n==I2S_CLKSEL_MCLK))
240 #define PARAM_I2S_4PIN(n) ((n==I2S_4PIN_ENABLE)||(n==I2S_4PIN_DISABLE))
242 #define PARAM_I2S_MCLK(n) ((n==I2S_MCLK_ENABLE)||(n==I2S_MCLK_DISABLE))
244 #define PARAM_I2S_DMA(n) ((n==I2S_DMA_1)||(n==I2S_DMA_2))
246 #define PARAM_I2S_DMA_DEPTH(n) ((n>=0)||(n<=31))
248 #define PARAM_I2S_IRQ_LEVEL(n) ((n>=0)||(n<=31))
250 #define PARAM_I2S_HALFPERIOD(n) ((n>0)&&(n<512))
252 #define PARAM_I2S_BITRATE(n) ((n>=0)&&(n<=63))
287 uint8_t Reserved0[2];
298 uint8_t Reserved0[2];