Macros
#define	PWM_IR_PWMMRn(n) ((uint32_t)((n<4)?(1<<n):(1<<(n+4))))

#define	PWM_IR_PWMCAPn(n) ((uint32_t)(1<<(n+4)))

#define	PWM_IR_BITMASK ((uint32_t)(0x0000073F))

#define	PWM_TCR_BITMASK ((uint32_t)(0x0000000B))

#define	PWM_TCR_COUNTER_ENABLE ((uint32_t)(1<<0))

#define	PWM_TCR_COUNTER_RESET ((uint32_t)(1<<1))

#define	PWM_TCR_PWM_ENABLE ((uint32_t)(1<<3))

#define	PWM_CTCR_BITMASK ((uint32_t)(0x0000000F))

#define	PWM_CTCR_MODE(n) ((uint32_t)(n&0x03))

#define	PWM_CTCR_SELECT_INPUT(n) ((uint32_t)((n&0x03)<<2))

#define	PWM_MCR_BITMASK ((uint32_t)(0x001FFFFF))

#define	PWM_MCR_INT_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07))))

#define	PWM_MCR_RESET_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+1)))

#define	PWM_MCR_STOP_ON_MATCH(n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+2)))

#define	PWM_CCR_BITMASK ((uint32_t)(0x0000003F))

#define	PWM_CCR_CAP_RISING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1))))

#define	PWM_CCR_CAP_FALLING(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+1)))

#define	PWM_CCR_INT_ON_CAP(n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+2)))

#define	PWM_PCR_BITMASK (uint32_t)0x00007E7C

#define	PWM_PCR_PWMSELn(n) ((uint32_t)(((n&0x7)<2) ? 0 : (1<<n)))

#define	PWM_PCR_PWMENAn(n) ((uint32_t)(((n&0x7)<1) ? 0 : (1<<(n+8))))

#define	PWM_LER_BITMASK ((uint32_t)(0x0000007F))

#define	PWM_LER_EN_MATCHn_LATCH(n) ((uint32_t)((n<7) ? (1<<n) : 0))

#define	PARAM_PWMx(n) (((uint32_t )n)==((uint32_t )LPC_PWM1))

#define	PARAM_PWM1_MATCH_CHANNEL(n) ((n>=0) && (n<=6))

#define	PARAM_PWM1_CHANNEL(n) ((n>=1) && (n<=6))

#define	PARAM_PWM1_EDGE_MODE_CHANNEL(n) ((n>=2) && (n<=6))

#define	PARAM_PWM1_CAPTURE_CHANNEL(n) ((n==0) \|\| (n==1))

#define	PARAM_PWM_INTSTAT(n)

Detailed Description

Macro Definition Documentation

#define PARAM_PWM1_CAPTURE_CHANNEL ( n) ((n==0) || (n==1))

Macro check PWM1 capture channel mode

Definition at line 132 of file lpc17xx_pwm.h.

#define PARAM_PWM1_CHANNEL ( n) ((n>=1) && (n<=6))

Macro check PWM1 channel value

Definition at line 126 of file lpc17xx_pwm.h.

#define PARAM_PWM1_EDGE_MODE_CHANNEL ( n) ((n>=2) && (n<=6))

Macro check PWM1 edge channel mode

Definition at line 129 of file lpc17xx_pwm.h.

#define PARAM_PWM1_MATCH_CHANNEL ( n) ((n>=0) && (n<=6))

Macro check PWM1 match channel value

Definition at line 123 of file lpc17xx_pwm.h.

#define PARAM_PWM_INTSTAT ( n)

Value:

((n==PWM_INTSTAT_MR0) || (n==PWM_INTSTAT_MR1) || (n==PWM_INTSTAT_MR2) \
|| (n==PWM_INTSTAT_MR3) || (n==PWM_INTSTAT_MR4) || (n==PWM_INTSTAT_MR5) \
|| (n==PWM_INTSTAT_MR6) || (n==PWM_INTSTAT_CAP0) || (n==PWM_INTSTAT_CAP1))

Macro check PWM1 interrupt status type

Definition at line 135 of file lpc17xx_pwm.h.

#define PARAM_PWMx ( n) (((uint32_t *)n)==((uint32_t *)LPC_PWM1))

Macro to determine if it is valid PWM peripheral or not

Definition at line 120 of file lpc17xx_pwm.h.

#define PWM_CCR_BITMASK ((uint32_t)(0x0000003F))

CCR register mask

Definition at line 92 of file lpc17xx_pwm.h.

#define PWM_CCR_CAP_FALLING ( n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+1)))

PCAPn is falling edge sensitive

Definition at line 96 of file lpc17xx_pwm.h.

#define PWM_CCR_CAP_RISING ( n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1))))

PCAPn is rising edge sensitive

Definition at line 94 of file lpc17xx_pwm.h.

#define PWM_CCR_INT_ON_CAP ( n) ((uint32_t)(1<<(((n&0x2)<<1)+(n&0x1)+2)))

PWM interrupt is generated on a PCAP event

Definition at line 98 of file lpc17xx_pwm.h.

#define PWM_CTCR_BITMASK ((uint32_t)(0x0000000F))

CTCR register mask

Definition at line 70 of file lpc17xx_pwm.h.

#define PWM_CTCR_MODE ( n) ((uint32_t)(n&0x03))

PWM Counter-Timer Mode

Definition at line 72 of file lpc17xx_pwm.h.

#define PWM_CTCR_SELECT_INPUT ( n) ((uint32_t)((n&0x03)<<2))

PWM Capture input select

Definition at line 74 of file lpc17xx_pwm.h.

#define PWM_IR_BITMASK ((uint32_t)(0x0000073F))

IR register mask

Definition at line 55 of file lpc17xx_pwm.h.

#define PWM_IR_PWMCAPn ( n) ((uint32_t)(1<<(n+4)))

Interrupt flag for capture input

Definition at line 53 of file lpc17xx_pwm.h.

#define PWM_IR_PWMMRn ( n) ((uint32_t)((n<4)?(1<<n):(1<<(n+4))))

Interrupt flag for PWM match channel for 6 channel

Definition at line 51 of file lpc17xx_pwm.h.

#define PWM_LER_BITMASK ((uint32_t)(0x0000007F))

LER register mask

Definition at line 114 of file lpc17xx_pwm.h.

#define PWM_LER_EN_MATCHn_LATCH ( n) ((uint32_t)((n<7) ? (1<<n) : 0))

PWM MATCHn register update control

Definition at line 116 of file lpc17xx_pwm.h.

#define PWM_MCR_BITMASK ((uint32_t)(0x001FFFFF))

MCR register mask

Definition at line 80 of file lpc17xx_pwm.h.

#define PWM_MCR_INT_ON_MATCH ( n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07))))

generate a PWM interrupt when a MATCHn occurs

Definition at line 82 of file lpc17xx_pwm.h.

#define PWM_MCR_RESET_ON_MATCH ( n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+1)))

reset the PWM when a MATCHn occurs

Definition at line 84 of file lpc17xx_pwm.h.

#define PWM_MCR_STOP_ON_MATCH ( n) ((uint32_t)(1<<(((n&0x7)<<1)+(n&0x07)+2)))

stop the PWM when a MATCHn occurs

Definition at line 86 of file lpc17xx_pwm.h.

#define PWM_PCR_BITMASK (uint32_t)0x00007E7C

PCR register mask

Definition at line 104 of file lpc17xx_pwm.h.

#define PWM_PCR_PWMENAn ( n) ((uint32_t)(((n&0x7)<1) ? 0 : (1<<(n+8))))

enable PWM output n

Definition at line 108 of file lpc17xx_pwm.h.

#define PWM_PCR_PWMSELn ( n) ((uint32_t)(((n&0x7)<2) ? 0 : (1<<n)))

PWM output n is a single edge controlled output

Definition at line 106 of file lpc17xx_pwm.h.

#define PWM_TCR_BITMASK ((uint32_t)(0x0000000B))

TCR register mask

Definition at line 61 of file lpc17xx_pwm.h.

#define PWM_TCR_COUNTER_ENABLE ((uint32_t)(1<<0))

PWM Counter Enable

Definition at line 62 of file lpc17xx_pwm.h.

#define PWM_TCR_COUNTER_RESET ((uint32_t)(1<<1))

PWM Counter Reset

Definition at line 63 of file lpc17xx_pwm.h.

#define PWM_TCR_PWM_ENABLE ((uint32_t)(1<<3))

PWM Enable

Definition at line 64 of file lpc17xx_pwm.h.

Macros

Detailed Description

Macro Definition Documentation