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uc-sdk
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uc-sdk
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Macros | |
| #define | MCPWM_CON_RUN(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+0))) : (0)) |
| #define | MCPWM_CON_CENTER(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+1))) : (0)) |
| #define | MCPWM_CON_POLAR(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+2))) : (0)) |
| #define | MCPWM_CON_DTE(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+3))) : (0)) |
| #define | MCPWM_CON_DISUP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+4))) : (0)) |
| #define | MCPWM_CON_INVBDC ((uint32_t)(1<<29)) |
| #define | MCPWM_CON_ACMODE ((uint32_t)(1<<30)) |
| #define | MCPWM_CON_DCMODE ((uint32_t)(1<<31)) |
| #define | MCPWM_CAPCON_CAPMCI_RE(cap, mci) (((cap>=0)&&(cap<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0)) |
| #define | MCPWM_CAPCON_CAPMCI_FE(cap, mci) (((cap>=0)&&(cap<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0)) |
| #define | MCPWM_CAPCON_RT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<(18+(n)))) : (0)) |
| #define | MCPWM_CAPCON_HNFCAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<(21+(n)))) : (0)) |
| #define | MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0)) |
| #define | MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0)) |
| #define | MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0)) |
| #define | MCPWM_INT_ABORT ((uint32_t)(1<<15)) |
| #define | MCPWM_CNTCON_TCMCI_RE(tc, mci) (((tc>=0)&&(tc<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0)) |
| #define | MCPWM_CNTCON_TCMCI_FE(tc, mci) (((tc>=0)&&(tc<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0)) |
| #define | MCPWM_CNTCON_CNTR(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<(29+n))) : (0)) |
| #define | MCPWM_DT(n, x) (((n>=0)&&(n<=2)) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0)) |
| #define | MCPWM_CP_A0 ((uint32_t)(1<<0)) |
| #define | MCPWM_CP_B0 ((uint32_t)(1<<1)) |
| #define | MCPWM_CP_A1 ((uint32_t)(1<<2)) |
| #define | MCPWM_CP_B1 ((uint32_t)(1<<3)) |
| #define | MCPWM_CP_A2 ((uint32_t)(1<<4)) |
| #define | MCPWM_CP_B2 ((uint32_t)(1<<5)) |
| #define | MCPWM_CAPCLR_CAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<n)) : (0)) |
| #define MCPWM_CAPCLR_CAP | ( | n) | (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<n)) : (0)) |
Macro defines for MCPWM Capture clear address registerClear the MCCAP (n) register
Definition at line 192 of file lpc17xx_mcpwm.h.
| #define MCPWM_CAPCON_CAPMCI_FE | ( | cap, | |
| mci | |||
| ) | (((cap>=0)&&(cap<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0)) |
Enables/Disable channel (cap) capture event on a falling edge on MCI(mci)
Definition at line 129 of file lpc17xx_mcpwm.h.
| #define MCPWM_CAPCON_CAPMCI_RE | ( | cap, | |
| mci | |||
| ) | (((cap>=0)&&(cap<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0)) |
Macro defines for MCPWM Capture Control registerEnables/Disable channel (cap) capture event on a rising edge on MCI(mci)
Definition at line 127 of file lpc17xx_mcpwm.h.
| #define MCPWM_CAPCON_HNFCAP | ( | n) | (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<(21+(n)))) : (0)) |
Hardware noise filter: channel (n) capture events are delayed
Definition at line 133 of file lpc17xx_mcpwm.h.
| #define MCPWM_CAPCON_RT | ( | n) | (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<(18+(n)))) : (0)) |
TC(n) is reset by channel (n) capture event
Definition at line 131 of file lpc17xx_mcpwm.h.
| #define MCPWM_CNTCON_CNTR | ( | n) | (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<(29+n))) : (0)) |
Channel (n) is in counter mode
Definition at line 170 of file lpc17xx_mcpwm.h.
| #define MCPWM_CNTCON_TCMCI_FE | ( | tc, | |
| mci | |||
| ) | (((tc>=0)&&(tc<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0)) |
Counter(cnt) advances on a falling edge on MCI(mci) pin
Definition at line 168 of file lpc17xx_mcpwm.h.
| #define MCPWM_CNTCON_TCMCI_RE | ( | tc, | |
| mci | |||
| ) | (((tc>=0)&&(tc<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0)) |
Macro defines for MCPWM Count Control registerCounter(tc) advances on a rising edge on MCI(mci) pin
Definition at line 166 of file lpc17xx_mcpwm.h.
| #define MCPWM_CON_ACMODE ((uint32_t)(1<<30)) |
3-phase AC mode select
Definition at line 114 of file lpc17xx_mcpwm.h.
| #define MCPWM_CON_CENTER | ( | n) | (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+1))) : (0)) |
Edge/center aligned operation for channel n
Definition at line 109 of file lpc17xx_mcpwm.h.
| #define MCPWM_CON_DCMODE ((uint32_t)(1<<31)) |
3-phase DC mode select
Definition at line 115 of file lpc17xx_mcpwm.h.
| #define MCPWM_CON_DISUP | ( | n) | (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+4))) : (0)) |
Enable/Disable update of functional register for channel n
Definition at line 112 of file lpc17xx_mcpwm.h.
| #define MCPWM_CON_DTE | ( | n) | (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+3))) : (0)) |
Control the dead-time feature for channel n
Definition at line 111 of file lpc17xx_mcpwm.h.
| #define MCPWM_CON_INVBDC ((uint32_t)(1<<29)) |
Control the polarity for all 3 channels
Definition at line 113 of file lpc17xx_mcpwm.h.
| #define MCPWM_CON_POLAR | ( | n) | (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+2))) : (0)) |
Select polarity of the MCOAn and MCOBn pin
Definition at line 110 of file lpc17xx_mcpwm.h.
| #define MCPWM_CON_RUN | ( | n) | (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+0))) : (0)) |
Macro defines for MCPWM Control registerStops/starts timer channel n
Definition at line 108 of file lpc17xx_mcpwm.h.
| #define MCPWM_CP_A0 ((uint32_t)(1<<0)) |
Macro defines for MCPWM Communication Pattern registerMCOA0 tracks internal MCOA0
Definition at line 181 of file lpc17xx_mcpwm.h.
| #define MCPWM_CP_A1 ((uint32_t)(1<<2)) |
MCOA1 tracks internal MCOA0
Definition at line 183 of file lpc17xx_mcpwm.h.
| #define MCPWM_CP_A2 ((uint32_t)(1<<4)) |
MCOA2 tracks internal MCOA0
Definition at line 185 of file lpc17xx_mcpwm.h.
| #define MCPWM_CP_B0 ((uint32_t)(1<<1)) |
MCOB0 tracks internal MCOA0
Definition at line 182 of file lpc17xx_mcpwm.h.
| #define MCPWM_CP_B1 ((uint32_t)(1<<3)) |
MCOB1 tracks internal MCOA0
Definition at line 184 of file lpc17xx_mcpwm.h.
| #define MCPWM_CP_B2 ((uint32_t)(1<<5)) |
MCOB2 tracks internal MCOA0
Definition at line 186 of file lpc17xx_mcpwm.h.
| #define MCPWM_DT | ( | n, | |
| x | |||
| ) | (((n>=0)&&(n<=2)) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0)) |
Macro defines for MCPWM Dead-time registerDead time value x for channel n
Definition at line 176 of file lpc17xx_mcpwm.h.
| #define MCPWM_INT_ABORT ((uint32_t)(1<<15)) |
Fast abort interrupt
Definition at line 154 of file lpc17xx_mcpwm.h.
| #define MCPWM_INT_ICAP | ( | n) | (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0)) |
Capture interrupt for channel (n)
Definition at line 152 of file lpc17xx_mcpwm.h.
| #define MCPWM_INT_ILIM | ( | n) | (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0)) |
Macro defines for MCPWM Interrupt registerLimit interrupt for channel (n)
Definition at line 148 of file lpc17xx_mcpwm.h.
| #define MCPWM_INT_IMAT | ( | n) | (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0)) |
Match interrupt for channel (n)
Definition at line 150 of file lpc17xx_mcpwm.h.
1.8.4 
