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lpc17xx_mcpwm.h
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1 /***********************************************************************/
21 /* Peripheral group ----------------------------------------------------------- */
27 #ifndef LPC17XX_MCPWM_H_
28 #define LPC17XX_MCPWM_H_
29 
30 /* Includes ------------------------------------------------------------------- */
31 #include "LPC17xx.h"
32 #include "lpc_types.h"
33 
34 
35 #ifdef __cplusplus
36 extern "C"
37 {
38 #endif
39 
40 /* Public Macros -------------------------------------------------------------- */
47 #define MCPWM_CHANNEL_EDGE_MODE ((uint32_t)(0))
48 
49 #define MCPWM_CHANNEL_CENTER_MODE ((uint32_t)(1))
50 
52 #define MCPWM_CHANNEL_PASSIVE_LO ((uint32_t)(0))
53 
54 #define MCPWM_CHANNEL_PASSIVE_HI ((uint32_t)(1))
55 
56 /* Output Patent in 3-phase DC mode, the internal MCOA0 signal is routed to any or all of
57  * the six output pins under the control of the bits in this register */
58 #define MCPWM_PATENT_A0 ((uint32_t)(1<<0))
59 #define MCPWM_PATENT_B0 ((uint32_t)(1<<1))
60 #define MCPWM_PATENT_A1 ((uint32_t)(1<<2))
61 #define MCPWM_PATENT_B1 ((uint32_t)(1<<3))
62 #define MCPWM_PATENT_A2 ((uint32_t)(1<<4))
63 #define MCPWM_PATENT_B2 ((uint32_t)(1<<5))
65 /* Interrupt type in MCPWM */
66 
67 #define MCPWM_INTFLAG_LIM0 MCPWM_INT_ILIM(0)
68 
69 #define MCPWM_INTFLAG_MAT0 MCPWM_INT_IMAT(0)
70 
71 #define MCPWM_INTFLAG_CAP0 MCPWM_INT_ICAP(0)
72 
74 #define MCPWM_INTFLAG_LIM1 MCPWM_INT_ILIM(1)
75 
76 #define MCPWM_INTFLAG_MAT1 MCPWM_INT_IMAT(1)
77 
78 #define MCPWM_INTFLAG_CAP1 MCPWM_INT_ICAP(1)
79 
81 #define MCPWM_INTFLAG_LIM2 MCPWM_INT_ILIM(2)
82 
83 #define MCPWM_INTFLAG_MAT2 MCPWM_INT_IMAT(2)
84 
85 #define MCPWM_INTFLAG_CAP2 MCPWM_INT_ICAP(2)
86 
88 #define MCPWM_INTFLAG_ABORT MCPWM_INT_ABORT
89 
94 /* Private Macros ------------------------------------------------------------- */
99 /*********************************************************************/
102 /* MCPWM Control register, these macro definitions below can be applied for these
103  * register type:
104  * - MCPWM Control read address
105  * - MCPWM Control set address
106  * - MCPWM Control clear address
107  */
108 #define MCPWM_CON_RUN(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+0))) : (0))
109 #define MCPWM_CON_CENTER(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+1))) : (0))
110 #define MCPWM_CON_POLAR(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+2))) : (0))
111 #define MCPWM_CON_DTE(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+3))) : (0))
112 #define MCPWM_CON_DISUP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*8)+4))) : (0))
113 #define MCPWM_CON_INVBDC ((uint32_t)(1<<29))
114 #define MCPWM_CON_ACMODE ((uint32_t)(1<<30))
115 #define MCPWM_CON_DCMODE ((uint32_t)(1<<31))
117 /*********************************************************************/
120 /* Capture Control register, these macro definitions below can be applied for these
121  * register type:
122  * - MCPWM Capture Control read address
123  * - MCPWM Capture Control set address
124  * - MCPWM Capture control clear address
125  */
126 
127 #define MCPWM_CAPCON_CAPMCI_RE(cap,mci) (((cap>=0)&&(cap<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+0))) : (0))
128 
129 #define MCPWM_CAPCON_CAPMCI_FE(cap,mci) (((cap>=0)&&(cap<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((cap*6)+(mci*2)+1))) : (0))
130 
131 #define MCPWM_CAPCON_RT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<(18+(n)))) : (0))
132 
133 #define MCPWM_CAPCON_HNFCAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<(21+(n)))) : (0))
134 
135 /*********************************************************************/
138 /* Interrupt registers, these macro definitions below can be applied for these
139  * register type:
140  * - MCPWM Interrupt Enable read address
141  * - MCPWM Interrupt Enable set address
142  * - MCPWM Interrupt Enable clear address
143  * - MCPWM Interrupt Flags read address
144  * - MCPWM Interrupt Flags set address
145  * - MCPWM Interrupt Flags clear address
146  */
148 #define MCPWM_INT_ILIM(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+0))) : (0))
149 
150 #define MCPWM_INT_IMAT(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+1))) : (0))
151 
152 #define MCPWM_INT_ICAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<((n*4)+2))) : (0))
153 
154 #define MCPWM_INT_ABORT ((uint32_t)(1<<15))
155 
156 /*********************************************************************/
159 /* MCPWM Count Control register, these macro definitions below can be applied for these
160  * register type:
161  * - MCPWM Count Control read address
162  * - MCPWM Count Control set address
163  * - MCPWM Count Control clear address
164  */
166 #define MCPWM_CNTCON_TCMCI_RE(tc,mci) (((tc>=0)&&(tc<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+0))) : (0))
167 
168 #define MCPWM_CNTCON_TCMCI_FE(tc,mci) (((tc>=0)&&(tc<=2)&&(mci>=0)&&(mci<=2)) ? ((uint32_t)(1<<((6*tc)+(2*mci)+1))) : (0))
169 
170 #define MCPWM_CNTCON_CNTR(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<(29+n))) : (0))
171 
172 /*********************************************************************/
176 #define MCPWM_DT(n,x) (((n>=0)&&(n<=2)) ? ((uint32_t)((x&0x3FF)<<(n*10))) : (0))
177 
178 /*********************************************************************/
181 #define MCPWM_CP_A0 ((uint32_t)(1<<0))
182 #define MCPWM_CP_B0 ((uint32_t)(1<<1))
183 #define MCPWM_CP_A1 ((uint32_t)(1<<2))
184 #define MCPWM_CP_B1 ((uint32_t)(1<<3))
185 #define MCPWM_CP_A2 ((uint32_t)(1<<4))
186 #define MCPWM_CP_B2 ((uint32_t)(1<<5))
188 /*********************************************************************/
192 #define MCPWM_CAPCLR_CAP(n) (((n>=0)&&(n<=2)) ? ((uint32_t)(1<<n)) : (0))
193 
194 
200 /* Public Types --------------------------------------------------------------- */
208 typedef struct {
209  uint32_t channelType;
214  uint32_t channelPolarity;
218  uint32_t channelDeadtimeEnable;
222  uint32_t channelDeadtimeValue;
223  uint32_t channelUpdateEnable;
228  uint32_t channelTimercounterValue;
229  uint32_t channelPeriodValue;
230  uint32_t channelPulsewidthValue;
231 } MCPWM_CHANNEL_CFG_Type;
232 
236 typedef struct {
237  uint32_t captureChannel;
238  uint32_t captureRising;
242  uint32_t captureFalling;
246  uint32_t timerReset;
250  uint32_t hnfEnable;
254 } MCPWM_CAPTURE_CFG_Type;
255 
256 
260 typedef struct {
261  uint32_t counterChannel;
262  uint32_t countRising;
266  uint32_t countFalling;
270 } MCPWM_COUNT_CFG_Type;
271 
277 /* Public Functions ----------------------------------------------------------- */
282 void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx);
283 void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
284  MCPWM_CHANNEL_CFG_Type * channelSetup);
285 void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
286  MCPWM_CHANNEL_CFG_Type *channelSetup);
287 void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
288  MCPWM_CAPTURE_CFG_Type *captureConfig);
289 void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
290 uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel);
291 void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
292  uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig);
293 void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
294 void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx,uint32_t channel0, uint32_t channel1, uint32_t channel2);
295 void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx,uint32_t acMode);
296 void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode,
297  uint32_t outputInvered, uint32_t outputPattern);
298 void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState);
299 void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
300 void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
301 FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType);
302 
307 #ifdef __cplusplus
308 }
309 #endif
310 
311 #endif /* LPC17XX_MCPWM_H_ */
312 
317 /* --------------------------------- End Of File ------------------------------ */