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EMAC Private Macros

Macros

#define EMAC_NUM_RX_FRAG   4
 
#define EMAC_NUM_TX_FRAG   3
 
#define EMAC_ETH_MAX_FLEN   1536
 
#define EMAC_TX_FRAME_TOUT   0x00100000
 
#define EMAC_MAC1_REC_EN   0x00000001
 
#define EMAC_MAC1_PASS_ALL   0x00000002
 
#define EMAC_MAC1_RX_FLOWC   0x00000004
 
#define EMAC_MAC1_TX_FLOWC   0x00000008
 
#define EMAC_MAC1_LOOPB   0x00000010
 
#define EMAC_MAC1_RES_TX   0x00000100
 
#define EMAC_MAC1_RES_MCS_TX   0x00000200
 
#define EMAC_MAC1_RES_RX   0x00000400
 
#define EMAC_MAC1_RES_MCS_RX   0x00000800
 
#define EMAC_MAC1_SIM_RES   0x00004000
 
#define EMAC_MAC1_SOFT_RES   0x00008000
 
#define EMAC_MAC2_FULL_DUP   0x00000001
 
#define EMAC_MAC2_FRM_LEN_CHK   0x00000002
 
#define EMAC_MAC2_HUGE_FRM_EN   0x00000004
 
#define EMAC_MAC2_DLY_CRC   0x00000008
 
#define EMAC_MAC2_CRC_EN   0x00000010
 
#define EMAC_MAC2_PAD_EN   0x00000020
 
#define EMAC_MAC2_VLAN_PAD_EN   0x00000040
 
#define EMAC_MAC2_ADET_PAD_EN   0x00000080
 
#define EMAC_MAC2_PPREAM_ENF   0x00000100
 
#define EMAC_MAC2_LPREAM_ENF   0x00000200
 
#define EMAC_MAC2_NO_BACKOFF   0x00001000
 
#define EMAC_MAC2_BACK_PRESSURE   0x00002000
 
#define EMAC_MAC2_EXCESS_DEF   0x00004000
 
#define EMAC_IPGT_BBIPG(n)   (n&0x7F)
 
#define EMAC_IPGT_FULL_DUP   (EMAC_IPGT_BBIPG(0x15))
 
#define EMAC_IPGT_HALF_DUP   (EMAC_IPGT_BBIPG(0x12))
 
#define EMAC_IPGR_NBBIPG_P2(n)   (n&0x7F)
 
#define EMAC_IPGR_P2_DEF   (EMAC_IPGR_NBBIPG_P2(0x12))
 
#define EMAC_IPGR_NBBIPG_P1(n)   ((n&0x7F)<<8)
 
#define EMAC_IPGR_P1_DEF   EMAC_IPGR_NBBIPG_P1(0x0C)
 
#define EMAC_CLRT_MAX_RETX(n)   (n&0x0F)
 
#define EMAC_CLRT_COLL(n)   ((n&0x3F)<<8)
 
#define EMAC_CLRT_DEF   ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
 
#define EMAC_MAXF_MAXFRMLEN(n)   (n&0xFFFF)
 
#define EMAC_SUPP_SPEED   0x00000100
 
#define EMAC_SUPP_RES_RMII   0x00000800
 
#define EMAC_TEST_SHCUT_PQUANTA   0x00000001
 
#define EMAC_TEST_TST_PAUSE   0x00000002
 
#define EMAC_TEST_TST_BACKP   0x00000004
 
#define EMAC_MCFG_SCAN_INC   0x00000001
 
#define EMAC_MCFG_SUPP_PREAM   0x00000002
 
#define EMAC_MCFG_CLK_SEL(n)   ((n&0x0F)<<2)
 
#define EMAC_MCFG_RES_MII   0x00008000
 
#define EMAC_MCFG_MII_MAXCLK   2500000UL
 
#define EMAC_MCMD_READ   0x00000001
 
#define EMAC_MCMD_SCAN   0x00000002
 
#define EMAC_MII_WR_TOUT   0x00050000
 
#define EMAC_MII_RD_TOUT   0x00050000
 
#define EMAC_MADR_REG_ADR(n)   (n&0x1F)
 
#define EMAC_MADR_PHY_ADR(n)   ((n&0x1F)<<8)
 
#define EMAC_MWTD_DATA(n)   (n&0xFFFF)
 
#define EMAC_MRDD_DATA(n)   (n&0xFFFF)
 
#define EMAC_MIND_BUSY   0x00000001
 
#define EMAC_MIND_SCAN   0x00000002
 
#define EMAC_MIND_NOT_VAL   0x00000004
 
#define EMAC_MIND_MII_LINK_FAIL   0x00000008
 
#define EMAC_CR_RX_EN   0x00000001
 
#define EMAC_CR_TX_EN   0x00000002
 
#define EMAC_CR_REG_RES   0x00000008
 
#define EMAC_CR_TX_RES   0x00000010
 
#define EMAC_CR_RX_RES   0x00000020
 
#define EMAC_CR_PASS_RUNT_FRM   0x00000040
 
#define EMAC_CR_PASS_RX_FILT   0x00000080
 
#define EMAC_CR_TX_FLOW_CTRL   0x00000100
 
#define EMAC_CR_RMII   0x00000200
 
#define EMAC_CR_FULL_DUP   0x00000400
 
#define EMAC_SR_RX_EN   0x00000001
 
#define EMAC_SR_TX_EN   0x00000002
 
#define EMAC_TSV0_CRC_ERR   0x00000001
 
#define EMAC_TSV0_LEN_CHKERR   0x00000002
 
#define EMAC_TSV0_LEN_OUTRNG   0x00000004
 
#define EMAC_TSV0_DONE   0x00000008
 
#define EMAC_TSV0_MCAST   0x00000010
 
#define EMAC_TSV0_BCAST   0x00000020
 
#define EMAC_TSV0_PKT_DEFER   0x00000040
 
#define EMAC_TSV0_EXC_DEFER   0x00000080
 
#define EMAC_TSV0_EXC_COLL   0x00000100
 
#define EMAC_TSV0_LATE_COLL   0x00000200
 
#define EMAC_TSV0_GIANT   0x00000400
 
#define EMAC_TSV0_UNDERRUN   0x00000800
 
#define EMAC_TSV0_BYTES   0x0FFFF000
 
#define EMAC_TSV0_CTRL_FRAME   0x10000000
 
#define EMAC_TSV0_PAUSE   0x20000000
 
#define EMAC_TSV0_BACK_PRESS   0x40000000
 
#define EMAC_TSV0_VLAN   0x80000000
 
#define EMAC_TSV1_BYTE_CNT   0x0000FFFF
 
#define EMAC_TSV1_COLL_CNT   0x000F0000
 
#define EMAC_RSV_BYTE_CNT   0x0000FFFF
 
#define EMAC_RSV_PKT_IGNORED   0x00010000
 
#define EMAC_RSV_RXDV_SEEN   0x00020000
 
#define EMAC_RSV_CARR_SEEN   0x00040000
 
#define EMAC_RSV_REC_CODEV   0x00080000
 
#define EMAC_RSV_CRC_ERR   0x00100000
 
#define EMAC_RSV_LEN_CHKERR   0x00200000
 
#define EMAC_RSV_LEN_OUTRNG   0x00400000
 
#define EMAC_RSV_REC_OK   0x00800000
 
#define EMAC_RSV_MCAST   0x01000000
 
#define EMAC_RSV_BCAST   0x02000000
 
#define EMAC_RSV_DRIB_NIBB   0x04000000
 
#define EMAC_RSV_CTRL_FRAME   0x08000000
 
#define EMAC_RSV_PAUSE   0x10000000
 
#define EMAC_RSV_UNSUPP_OPC   0x20000000
 
#define EMAC_RSV_VLAN   0x40000000
 
#define EMAC_FCC_MIRR_CNT(n)   (n&0xFFFF)
 
#define EMAC_FCC_PAUSE_TIM(n)   ((n&0xFFFF)<<16)
 
#define EMAC_FCS_MIRR_CNT(n)   (n&0xFFFF)
 
#define EMAC_RFC_UCAST_EN   0x00000001
 
#define EMAC_RFC_BCAST_EN   0x00000002
 
#define EMAC_RFC_MCAST_EN   0x00000004
 
#define EMAC_RFC_UCAST_HASH_EN   0x00000008
 
#define EMAC_RFC_MCAST_HASH_EN   0x00000010
 
#define EMAC_RFC_PERFECT_EN   0x00000020
 
#define EMAC_RFC_MAGP_WOL_EN   0x00001000
 
#define EMAC_RFC_PFILT_WOL_EN   0x00002000
 
#define EMAC_WOL_UCAST   0x00000001
 
#define EMAC_WOL_BCAST   0x00000002
 
#define EMAC_WOL_MCAST   0x00000004
 
#define EMAC_WOL_UCAST_HASH   0x00000008
 
#define EMAC_WOL_MCAST_HASH   0x00000010
 
#define EMAC_WOL_PERFECT   0x00000020
 
#define EMAC_WOL_RX_FILTER   0x00000080
 
#define EMAC_WOL_MAG_PACKET   0x00000100
 
#define EMAC_WOL_BITMASK   0x01BF
 
#define EMAC_INT_RX_OVERRUN   0x00000001
 
#define EMAC_INT_RX_ERR   0x00000002
 
#define EMAC_INT_RX_FIN   0x00000004
 
#define EMAC_INT_RX_DONE   0x00000008
 
#define EMAC_INT_TX_UNDERRUN   0x00000010
 
#define EMAC_INT_TX_ERR   0x00000020
 
#define EMAC_INT_TX_FIN   0x00000040
 
#define EMAC_INT_TX_DONE   0x00000080
 
#define EMAC_INT_SOFT_INT   0x00001000
 
#define EMAC_INT_WAKEUP   0x00002000
 
#define EMAC_PD_POWER_DOWN   0x80000000
 
#define EMAC_RCTRL_SIZE(n)   (n&0x7FF)
 
#define EMAC_RCTRL_INT   0x80000000
 
#define EMAC_RHASH_SA   0x000001FF
 
#define EMAC_RHASH_DA   0x001FF000
 
#define EMAC_RINFO_SIZE   0x000007FF
 
#define EMAC_RINFO_CTRL_FRAME   0x00040000
 
#define EMAC_RINFO_VLAN   0x00080000
 
#define EMAC_RINFO_FAIL_FILT   0x00100000
 
#define EMAC_RINFO_MCAST   0x00200000
 
#define EMAC_RINFO_BCAST   0x00400000
 
#define EMAC_RINFO_CRC_ERR   0x00800000
 
#define EMAC_RINFO_SYM_ERR   0x01000000
 
#define EMAC_RINFO_LEN_ERR   0x02000000
 
#define EMAC_RINFO_RANGE_ERR   0x04000000
 
#define EMAC_RINFO_ALIGN_ERR   0x08000000
 
#define EMAC_RINFO_OVERRUN   0x10000000
 
#define EMAC_RINFO_NO_DESCR   0x20000000
 
#define EMAC_RINFO_LAST_FLAG   0x40000000
 
#define EMAC_RINFO_ERR   0x80000000
 
#define EMAC_RINFO_ERR_MASK
 
#define EMAC_TCTRL_SIZE   0x000007FF
 
#define EMAC_TCTRL_OVERRIDE   0x04000000
 
#define EMAC_TCTRL_HUGE   0x08000000
 
#define EMAC_TCTRL_PAD   0x10000000
 
#define EMAC_TCTRL_CRC   0x20000000
 
#define EMAC_TCTRL_LAST   0x40000000
 
#define EMAC_TCTRL_INT   0x80000000
 
#define EMAC_TINFO_COL_CNT   0x01E00000
 
#define EMAC_TINFO_DEFER   0x02000000
 
#define EMAC_TINFO_EXCESS_DEF   0x04000000
 
#define EMAC_TINFO_EXCESS_COL   0x08000000
 
#define EMAC_TINFO_LATE_COL   0x10000000
 
#define EMAC_TINFO_UNDERRUN   0x20000000
 
#define EMAC_TINFO_NO_DESCR   0x40000000
 
#define EMAC_TINFO_ERR   0x80000000
 
#define EMAC_PHY_RESP_TOUT   0x100000UL
 
#define EMAC_OLD_EMAC_MODULE_ID   0x39022000
 
#define EMAC_PHY_REG_BMCR   0x00
 
#define EMAC_PHY_REG_BMSR   0x01
 
#define EMAC_PHY_REG_IDR1   0x02
 
#define EMAC_PHY_REG_IDR2   0x03
 
#define EMAC_PHY_REG_ANAR   0x04
 
#define EMAC_PHY_REG_ANLPAR   0x05
 
#define EMAC_PHY_REG_ANER   0x06
 
#define EMAC_PHY_REG_ANNPTR   0x07
 
#define EMAC_PHY_REG_LPNPA   0x08
 
#define EMAC_PHY_REG_STS   0x10
 
#define EMAC_PHY_REG_MICR   0x11
 
#define EMAC_PHY_REG_MISR   0x12
 
#define EMAC_PHY_REG_FCSCR   0x14
 
#define EMAC_PHY_REG_RECR   0x15
 
#define EMAC_PHY_REG_PCSR   0x16
 
#define EMAC_PHY_REG_RBR   0x17
 
#define EMAC_PHY_REG_LEDCR   0x18
 
#define EMAC_PHY_REG_PHYCR   0x19
 
#define EMAC_PHY_REG_10BTSCR   0x1A
 
#define EMAC_PHY_REG_CDCTRL1   0x1B
 
#define EMAC_PHY_REG_EDCR   0x1D
 
#define EMAC_PHY_BMCR_RESET   (1<<15)
 
#define EMAC_PHY_BMCR_LOOPBACK   (1<<14)
 
#define EMAC_PHY_BMCR_SPEED_SEL   (1<<13)
 
#define EMAC_PHY_BMCR_AN   (1<<12)
 
#define EMAC_PHY_BMCR_POWERDOWN   (1<<11)
 
#define EMAC_PHY_BMCR_ISOLATE   (1<<10)
 
#define EMAC_PHY_BMCR_RE_AN   (1<<9)
 
#define EMAC_PHY_BMCR_DUPLEX   (1<<8)
 
#define EMAC_PHY_BMSR_100BE_T4   (1<<15)
 
#define EMAC_PHY_BMSR_100TX_FULL   (1<<14)
 
#define EMAC_PHY_BMSR_100TX_HALF   (1<<13)
 
#define EMAC_PHY_BMSR_10BE_FULL   (1<<12)
 
#define EMAC_PHY_BMSR_10BE_HALF   (1<<11)
 
#define EMAC_PHY_BMSR_NOPREAM   (1<<6)
 
#define EMAC_PHY_BMSR_AUTO_DONE   (1<<5)
 
#define EMAC_PHY_BMSR_REMOTE_FAULT   (1<<4)
 
#define EMAC_PHY_BMSR_NO_AUTO   (1<<3)
 
#define EMAC_PHY_BMSR_LINK_ESTABLISHED   (1<<2)
 
#define EMAC_PHY_SR_REMOTE_FAULT   (1<<6)
 
#define EMAC_PHY_SR_JABBER   (1<<5)
 
#define EMAC_PHY_SR_AUTO_DONE   (1<<4)
 
#define EMAC_PHY_SR_LOOPBACK   (1<<3)
 
#define EMAC_PHY_SR_DUP   (1<<2)
 
#define EMAC_PHY_SR_SPEED   (1<<1)
 
#define EMAC_PHY_SR_LINK   (1<<0)
 
#define EMAC_PHY_FULLD_100M   0x2100
 
#define EMAC_PHY_HALFD_100M   0x2000
 
#define EMAC_PHY_FULLD_10M   0x0100
 
#define EMAC_PHY_HALFD_10M   0x0000
 
#define EMAC_PHY_AUTO_NEG   0x3000
 
#define EMAC_DEF_ADR   0x0100
 
#define EMAC_DP83848C_ID   0x20005C90
 
#define EMAC_PHY_SR_100_SPEED   ((1<<14)|(1<<13))
 
#define EMAC_PHY_SR_FULL_DUP   ((1<<14)|(1<<12))
 
#define EMAC_PHY_BMSR_LINK_STATUS   (1<<2)
 

Detailed Description

Macro Definition Documentation

#define EMAC_CLRT_COLL (   n)    ((n&0x3F)<<8)

Programmable field representing the slot time or collision window during which collisions occur in properly configured networks

Definition at line 145 of file lpc17xx_emac.h.

#define EMAC_CLRT_DEF   ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))

Default value for Collision Window / Retry register

Definition at line 147 of file lpc17xx_emac.h.

#define EMAC_CLRT_MAX_RETX (   n)    (n&0x0F)

Macro defines for Collision Window/Retry Register Programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions

Definition at line 142 of file lpc17xx_emac.h.

#define EMAC_CR_FULL_DUP   0x00000400

Full Duplex

Definition at line 228 of file lpc17xx_emac.h.

#define EMAC_CR_PASS_RUNT_FRM   0x00000040

Pass Runt Frames

Definition at line 224 of file lpc17xx_emac.h.

#define EMAC_CR_PASS_RX_FILT   0x00000080

Pass RX Filter

Definition at line 225 of file lpc17xx_emac.h.

#define EMAC_CR_REG_RES   0x00000008

Reset Host Registers

Definition at line 221 of file lpc17xx_emac.h.

#define EMAC_CR_RMII   0x00000200

Reduced MII Interface

Definition at line 227 of file lpc17xx_emac.h.

#define EMAC_CR_RX_EN   0x00000001

Macro defines for Command RegisterEnable Receive

Definition at line 219 of file lpc17xx_emac.h.

#define EMAC_CR_RX_RES   0x00000020

Reset Receive Datapath

Definition at line 223 of file lpc17xx_emac.h.

#define EMAC_CR_TX_EN   0x00000002

Enable Transmit

Definition at line 220 of file lpc17xx_emac.h.

#define EMAC_CR_TX_FLOW_CTRL   0x00000100

TX Flow Control

Definition at line 226 of file lpc17xx_emac.h.

#define EMAC_CR_TX_RES   0x00000010

Reset Transmit Datapath

Definition at line 222 of file lpc17xx_emac.h.

#define EMAC_DEF_ADR   0x0100

Default PHY device address

Definition at line 480 of file lpc17xx_emac.h.

#define EMAC_DP83848C_ID   0x20005C90

PHY Identifier

Definition at line 481 of file lpc17xx_emac.h.

#define EMAC_ETH_MAX_FLEN   1536

Max. Ethernet Frame Size

Definition at line 73 of file lpc17xx_emac.h.

#define EMAC_FCC_MIRR_CNT (   n)    (n&0xFFFF)

Macro defines for Flow Control Counter RegisterMirror Counter

Definition at line 286 of file lpc17xx_emac.h.

#define EMAC_FCC_PAUSE_TIM (   n)    ((n&0xFFFF)<<16)

Pause Timer

Definition at line 287 of file lpc17xx_emac.h.

#define EMAC_FCS_MIRR_CNT (   n)    (n&0xFFFF)

Macro defines for Flow Control Status RegisterMirror Counter Current

Definition at line 292 of file lpc17xx_emac.h.

#define EMAC_INT_RX_DONE   0x00000008

Receive Done

Definition at line 329 of file lpc17xx_emac.h.

#define EMAC_INT_RX_ERR   0x00000002

Receive Error

Definition at line 327 of file lpc17xx_emac.h.

#define EMAC_INT_RX_FIN   0x00000004

RX Finished Process Descriptors

Definition at line 328 of file lpc17xx_emac.h.

#define EMAC_INT_RX_OVERRUN   0x00000001

Macro defines for Interrupt Status/Enable/Clear/Set RegistersOverrun Error in RX Queue

Definition at line 326 of file lpc17xx_emac.h.

#define EMAC_INT_SOFT_INT   0x00001000

Software Triggered Interrupt

Definition at line 334 of file lpc17xx_emac.h.

#define EMAC_INT_TX_DONE   0x00000080

Transmit Done

Definition at line 333 of file lpc17xx_emac.h.

#define EMAC_INT_TX_ERR   0x00000020

Transmit Error

Definition at line 331 of file lpc17xx_emac.h.

#define EMAC_INT_TX_FIN   0x00000040

TX Finished Process Descriptors

Definition at line 332 of file lpc17xx_emac.h.

#define EMAC_INT_TX_UNDERRUN   0x00000010

Transmit Underrun

Definition at line 330 of file lpc17xx_emac.h.

#define EMAC_INT_WAKEUP   0x00002000

Wakeup Event Interrupt

Definition at line 335 of file lpc17xx_emac.h.

#define EMAC_IPGR_NBBIPG_P1 (   n)    ((n&0x7F)<<8)

Programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'

Definition at line 133 of file lpc17xx_emac.h.

#define EMAC_IPGR_NBBIPG_P2 (   n)    (n&0x7F)

Macro defines for Non Back-to-Back Inter-Packet-Gap RegisterProgrammable field representing the Non-Back-to-Back Inter-Packet-Gap

Definition at line 128 of file lpc17xx_emac.h.

#define EMAC_IPGR_P1_DEF   EMAC_IPGR_NBBIPG_P1(0x0C)

Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2

Definition at line 135 of file lpc17xx_emac.h.

#define EMAC_IPGR_P2_DEF   (EMAC_IPGR_NBBIPG_P2(0x12))

Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1

Definition at line 130 of file lpc17xx_emac.h.

#define EMAC_IPGT_BBIPG (   n)    (n&0x7F)

Macro defines for Back-to-Back Inter-Packet-Gap Register Programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next

Definition at line 114 of file lpc17xx_emac.h.

#define EMAC_IPGT_FULL_DUP   (EMAC_IPGT_BBIPG(0x15))

Recommended value for Full Duplex of Programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next

Definition at line 118 of file lpc17xx_emac.h.

#define EMAC_IPGT_HALF_DUP   (EMAC_IPGT_BBIPG(0x12))

Recommended value for Half Duplex of Programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next

Definition at line 122 of file lpc17xx_emac.h.

#define EMAC_MAC1_LOOPB   0x00000010

Loop Back Mode

Definition at line 84 of file lpc17xx_emac.h.

#define EMAC_MAC1_PASS_ALL   0x00000002

Pass All Receive Frames

Definition at line 81 of file lpc17xx_emac.h.

#define EMAC_MAC1_REC_EN   0x00000001

Macro defines for MAC Configuration Register 1Receive Enable

Definition at line 80 of file lpc17xx_emac.h.

#define EMAC_MAC1_RES_MCS_RX   0x00000800

Reset MAC RX Control Sublayer

Definition at line 88 of file lpc17xx_emac.h.

#define EMAC_MAC1_RES_MCS_TX   0x00000200

Reset MAC TX Control Sublayer

Definition at line 86 of file lpc17xx_emac.h.

#define EMAC_MAC1_RES_RX   0x00000400

Reset RX Logic

Definition at line 87 of file lpc17xx_emac.h.

#define EMAC_MAC1_RES_TX   0x00000100

Reset TX Logic

Definition at line 85 of file lpc17xx_emac.h.

#define EMAC_MAC1_RX_FLOWC   0x00000004

RX Flow Control

Definition at line 82 of file lpc17xx_emac.h.

#define EMAC_MAC1_SIM_RES   0x00004000

Simulation Reset

Definition at line 89 of file lpc17xx_emac.h.

#define EMAC_MAC1_SOFT_RES   0x00008000

Soft Reset MAC

Definition at line 90 of file lpc17xx_emac.h.

#define EMAC_MAC1_TX_FLOWC   0x00000008

TX Flow Control

Definition at line 83 of file lpc17xx_emac.h.

#define EMAC_MAC2_ADET_PAD_EN   0x00000080

Auto Detect Pad Enable

Definition at line 102 of file lpc17xx_emac.h.

#define EMAC_MAC2_BACK_PRESSURE   0x00002000

Backoff Presurre / No Backoff

Definition at line 106 of file lpc17xx_emac.h.

#define EMAC_MAC2_CRC_EN   0x00000010

Append CRC to every Frame

Definition at line 99 of file lpc17xx_emac.h.

#define EMAC_MAC2_DLY_CRC   0x00000008

Delayed CRC Mode

Definition at line 98 of file lpc17xx_emac.h.

#define EMAC_MAC2_EXCESS_DEF   0x00004000

Excess Defer

Definition at line 107 of file lpc17xx_emac.h.

#define EMAC_MAC2_FRM_LEN_CHK   0x00000002

Frame Length Checking

Definition at line 96 of file lpc17xx_emac.h.

#define EMAC_MAC2_FULL_DUP   0x00000001

Macro defines for MAC Configuration Register 2Full-Duplex Mode

Definition at line 95 of file lpc17xx_emac.h.

#define EMAC_MAC2_HUGE_FRM_EN   0x00000004

Huge Frame Enable

Definition at line 97 of file lpc17xx_emac.h.

#define EMAC_MAC2_LPREAM_ENF   0x00000200

Long Preamble Enforcement

Definition at line 104 of file lpc17xx_emac.h.

#define EMAC_MAC2_NO_BACKOFF   0x00001000

No Backoff Algorithm

Definition at line 105 of file lpc17xx_emac.h.

#define EMAC_MAC2_PAD_EN   0x00000020

Pad all Short Frames

Definition at line 100 of file lpc17xx_emac.h.

#define EMAC_MAC2_PPREAM_ENF   0x00000100

Pure Preamble Enforcement

Definition at line 103 of file lpc17xx_emac.h.

#define EMAC_MAC2_VLAN_PAD_EN   0x00000040

VLAN Pad Enable

Definition at line 101 of file lpc17xx_emac.h.

#define EMAC_MADR_PHY_ADR (   n)    ((n&0x1F)<<8)

PHY Address Field

Definition at line 190 of file lpc17xx_emac.h.

#define EMAC_MADR_REG_ADR (   n)    (n&0x1F)

Macro defines for MII Management Address RegisterMII Register Address field

Definition at line 189 of file lpc17xx_emac.h.

#define EMAC_MAXF_MAXFRMLEN (   n)    (n&0xFFFF)

Macro defines for Maximum Frame RegisterRepresents a maximum receive frame of 1536 octets

Definition at line 153 of file lpc17xx_emac.h.

#define EMAC_MCFG_CLK_SEL (   n)    ((n&0x0F)<<2)

Clock Select Field

Definition at line 173 of file lpc17xx_emac.h.

#define EMAC_MCFG_MII_MAXCLK   2500000UL

MII Clock max

Definition at line 175 of file lpc17xx_emac.h.

#define EMAC_MCFG_RES_MII   0x00008000

Reset MII Management Hardware

Definition at line 174 of file lpc17xx_emac.h.

#define EMAC_MCFG_SCAN_INC   0x00000001

Macro defines for MII Management Configuration RegisterScan Increment PHY Address

Definition at line 171 of file lpc17xx_emac.h.

#define EMAC_MCFG_SUPP_PREAM   0x00000002

Suppress Preamble

Definition at line 172 of file lpc17xx_emac.h.

#define EMAC_MCMD_READ   0x00000001

Macro defines for MII Management Command RegisterMII Read

Definition at line 180 of file lpc17xx_emac.h.

#define EMAC_MCMD_SCAN   0x00000002

MII Scan continuously

Definition at line 181 of file lpc17xx_emac.h.

#define EMAC_MII_RD_TOUT   0x00050000

MII Read timeout count

Definition at line 184 of file lpc17xx_emac.h.

#define EMAC_MII_WR_TOUT   0x00050000

MII Write timeout count

Definition at line 183 of file lpc17xx_emac.h.

#define EMAC_MIND_BUSY   0x00000001

Macro defines for MII Management Indicators RegisterMII is Busy

Definition at line 205 of file lpc17xx_emac.h.

#define EMAC_MIND_MII_LINK_FAIL   0x00000008

MII Link Failed

Definition at line 208 of file lpc17xx_emac.h.

#define EMAC_MIND_NOT_VAL   0x00000004

MII Read Data not valid

Definition at line 207 of file lpc17xx_emac.h.

#define EMAC_MIND_SCAN   0x00000002

MII Scanning in Progress

Definition at line 206 of file lpc17xx_emac.h.

#define EMAC_MRDD_DATA (   n)    (n&0xFFFF)

Macro defines for MII Management Read Data RegisterData field for MMI Management Read Data register

Definition at line 200 of file lpc17xx_emac.h.

#define EMAC_MWTD_DATA (   n)    (n&0xFFFF)

Macro defines for MII Management Write Data RegisterData field for MMI Management Write Data register

Definition at line 195 of file lpc17xx_emac.h.

#define EMAC_NUM_RX_FRAG   4

Num.of RX Fragments 4*1536= 6.0kB

Definition at line 71 of file lpc17xx_emac.h.

#define EMAC_NUM_TX_FRAG   3

Num.of TX Fragments 3*1536= 4.6kB

Definition at line 72 of file lpc17xx_emac.h.

#define EMAC_OLD_EMAC_MODULE_ID   0x39022000

Rev. ID for first rev '-'

Definition at line 406 of file lpc17xx_emac.h.

#define EMAC_PD_POWER_DOWN   0x80000000

Macro defines for Power Down RegisterPower Down MAC

Definition at line 340 of file lpc17xx_emac.h.

#define EMAC_PHY_AUTO_NEG   0x3000

Select Auto Negotiation

Definition at line 478 of file lpc17xx_emac.h.

#define EMAC_PHY_BMCR_AN   (1<<12)

Auto Negotiation

Definition at line 443 of file lpc17xx_emac.h.

#define EMAC_PHY_BMCR_DUPLEX   (1<<8)

Duplex mode

Definition at line 447 of file lpc17xx_emac.h.

#define EMAC_PHY_BMCR_ISOLATE   (1<<10)

Isolate

Definition at line 445 of file lpc17xx_emac.h.

#define EMAC_PHY_BMCR_LOOPBACK   (1<<14)

Loop back

Definition at line 441 of file lpc17xx_emac.h.

#define EMAC_PHY_BMCR_POWERDOWN   (1<<11)

Power down mode

Definition at line 444 of file lpc17xx_emac.h.

#define EMAC_PHY_BMCR_RE_AN   (1<<9)

Restart auto negotiation

Definition at line 446 of file lpc17xx_emac.h.

#define EMAC_PHY_BMCR_RESET   (1<<15)

Macro defines for PHY Basic Mode Control RegisterReset bit

Definition at line 440 of file lpc17xx_emac.h.

#define EMAC_PHY_BMCR_SPEED_SEL   (1<<13)

Speed selection

Definition at line 442 of file lpc17xx_emac.h.

#define EMAC_PHY_BMSR_100BE_T4   (1<<15)

Macro defines for PHY Basic Mode Status Status Register100 base T4

Definition at line 452 of file lpc17xx_emac.h.

#define EMAC_PHY_BMSR_100TX_FULL   (1<<14)

100 base full duplex

Definition at line 453 of file lpc17xx_emac.h.

#define EMAC_PHY_BMSR_100TX_HALF   (1<<13)

100 base half duplex

Definition at line 454 of file lpc17xx_emac.h.

#define EMAC_PHY_BMSR_10BE_FULL   (1<<12)

10 base T full duplex

Definition at line 455 of file lpc17xx_emac.h.

#define EMAC_PHY_BMSR_10BE_HALF   (1<<11)

10 base T half duplex

Definition at line 456 of file lpc17xx_emac.h.

#define EMAC_PHY_BMSR_AUTO_DONE   (1<<5)

Auto negotiation complete

Definition at line 458 of file lpc17xx_emac.h.

#define EMAC_PHY_BMSR_LINK_ESTABLISHED   (1<<2)

Link status

Definition at line 461 of file lpc17xx_emac.h.

#define EMAC_PHY_BMSR_LINK_STATUS   (1<<2)

Link status

Definition at line 485 of file lpc17xx_emac.h.

#define EMAC_PHY_BMSR_NO_AUTO   (1<<3)

Auto Negotiation ability

Definition at line 460 of file lpc17xx_emac.h.

#define EMAC_PHY_BMSR_NOPREAM   (1<<6)

MF Preamable Supress

Definition at line 457 of file lpc17xx_emac.h.

#define EMAC_PHY_BMSR_REMOTE_FAULT   (1<<4)

Remote fault

Definition at line 459 of file lpc17xx_emac.h.

#define EMAC_PHY_FULLD_100M   0x2100

Full Duplex 100Mbit

Definition at line 474 of file lpc17xx_emac.h.

#define EMAC_PHY_FULLD_10M   0x0100

Full Duplex 10Mbit

Definition at line 476 of file lpc17xx_emac.h.

#define EMAC_PHY_HALFD_100M   0x2000

Half Duplex 100Mbit

Definition at line 475 of file lpc17xx_emac.h.

#define EMAC_PHY_HALFD_10M   0x0000

Half Duplex 10MBit

Definition at line 477 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_10BTSCR   0x1A

10Base-T Status/Control Register

Definition at line 433 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_ANAR   0x04

Auto-Negotiation Advertisement

Definition at line 415 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_ANER   0x06

Auto-Neg. Expansion Register

Definition at line 417 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_ANLPAR   0x05

Auto-Neg. Link Partner Abitily

Definition at line 416 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_ANNPTR   0x07

Auto-Neg. Next Page TX

Definition at line 418 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_BMCR   0x00

Macro defines for DP83848C PHY RegistersBasic Mode Control Register

Definition at line 411 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_BMSR   0x01

Basic Mode Status Register

Definition at line 412 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_CDCTRL1   0x1B

CD Test Control and BIST Extens.

Definition at line 434 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_EDCR   0x1D

Energy Detect Control Register

Definition at line 435 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_FCSCR   0x14

False Carrier Sense Counter

Definition at line 427 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_IDR1   0x02

PHY Identifier 1

Definition at line 413 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_IDR2   0x03

PHY Identifier 2

Definition at line 414 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_LEDCR   0x18

LED Direct Control Register

Definition at line 431 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_LPNPA   0x08

Definition at line 419 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_MICR   0x11

MII Interrupt Control Register

Definition at line 425 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_MISR   0x12

MII Interrupt Status Register

Definition at line 426 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_PCSR   0x16

PCS Sublayer Config. and Status

Definition at line 429 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_PHYCR   0x19

PHY Control Register

Definition at line 432 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_RBR   0x17

RMII and Bypass Register

Definition at line 430 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_RECR   0x15

Receive Error Counter

Definition at line 428 of file lpc17xx_emac.h.

#define EMAC_PHY_REG_STS   0x10

Macro defines for PHY Extended RegistersStatus Register

Definition at line 424 of file lpc17xx_emac.h.

#define EMAC_PHY_RESP_TOUT   0x100000UL

PHY device reset time out definition

Definition at line 403 of file lpc17xx_emac.h.

#define EMAC_PHY_SR_100_SPEED   ((1<<14)|(1<<13))

Definition at line 483 of file lpc17xx_emac.h.

#define EMAC_PHY_SR_AUTO_DONE   (1<<4)

Auto Negotiation complete

Definition at line 468 of file lpc17xx_emac.h.

#define EMAC_PHY_SR_DUP   (1<<2)

Duplex status

Definition at line 470 of file lpc17xx_emac.h.

#define EMAC_PHY_SR_FULL_DUP   ((1<<14)|(1<<12))

Definition at line 484 of file lpc17xx_emac.h.

#define EMAC_PHY_SR_JABBER   (1<<5)

Jabber detect

Definition at line 467 of file lpc17xx_emac.h.

#define EMAC_PHY_SR_LINK   (1<<0)

Link Status

Definition at line 472 of file lpc17xx_emac.h.

#define EMAC_PHY_SR_LOOPBACK   (1<<3)

Loop back status

Definition at line 469 of file lpc17xx_emac.h.

#define EMAC_PHY_SR_REMOTE_FAULT   (1<<6)

Macro defines for PHY Status RegisterRemote Fault

Definition at line 466 of file lpc17xx_emac.h.

#define EMAC_PHY_SR_SPEED   (1<<1)

Speed status

Definition at line 471 of file lpc17xx_emac.h.

#define EMAC_RCTRL_INT   0x80000000

Generate RxDone Interrupt

Definition at line 347 of file lpc17xx_emac.h.

#define EMAC_RCTRL_SIZE (   n)    (n&0x7FF)

Macro defines for RX Descriptor Control WordBuffer size field

Definition at line 346 of file lpc17xx_emac.h.

#define EMAC_RFC_BCAST_EN   0x00000002

Accept Broadcast Frames Enable

Definition at line 300 of file lpc17xx_emac.h.

#define EMAC_RFC_MAGP_WOL_EN   0x00001000

Magic Packet Filter WoL Enable

Definition at line 305 of file lpc17xx_emac.h.

#define EMAC_RFC_MCAST_EN   0x00000004

Accept Multicast Frames Enable

Definition at line 301 of file lpc17xx_emac.h.

#define EMAC_RFC_MCAST_HASH_EN   0x00000010

Accept Multicast Hash Filter Fram.

Definition at line 303 of file lpc17xx_emac.h.

#define EMAC_RFC_PERFECT_EN   0x00000020

Accept Perfect Match Enable

Definition at line 304 of file lpc17xx_emac.h.

#define EMAC_RFC_PFILT_WOL_EN   0x00002000

Perfect Filter WoL Enable

Definition at line 306 of file lpc17xx_emac.h.

#define EMAC_RFC_UCAST_EN   0x00000001

Macro defines for Receive Filter Control RegisterAccept Unicast Frames Enable

Definition at line 299 of file lpc17xx_emac.h.

#define EMAC_RFC_UCAST_HASH_EN   0x00000008

Accept Unicast Hash Filter Frames

Definition at line 302 of file lpc17xx_emac.h.

#define EMAC_RHASH_DA   0x001FF000

Hash CRC for Destination Address

Definition at line 353 of file lpc17xx_emac.h.

#define EMAC_RHASH_SA   0x000001FF

Macro defines for RX Status Hash CRC WordHash CRC for Source Address

Definition at line 352 of file lpc17xx_emac.h.

#define EMAC_RINFO_ALIGN_ERR   0x08000000

Alignment Error

Definition at line 368 of file lpc17xx_emac.h.

#define EMAC_RINFO_BCAST   0x00400000

Broadcast Frame

Definition at line 363 of file lpc17xx_emac.h.

#define EMAC_RINFO_CRC_ERR   0x00800000

CRC Error in Frame

Definition at line 364 of file lpc17xx_emac.h.

#define EMAC_RINFO_CTRL_FRAME   0x00040000

Control Frame

Definition at line 359 of file lpc17xx_emac.h.

#define EMAC_RINFO_ERR   0x80000000

Error Occured (OR of all errors)

Definition at line 372 of file lpc17xx_emac.h.

#define EMAC_RINFO_ERR_MASK
Value:

Definition at line 373 of file lpc17xx_emac.h.

#define EMAC_RINFO_FAIL_FILT   0x00100000

RX Filter Failed

Definition at line 361 of file lpc17xx_emac.h.

#define EMAC_RINFO_LAST_FLAG   0x40000000

Last Fragment in Frame

Definition at line 371 of file lpc17xx_emac.h.

#define EMAC_RINFO_LEN_ERR   0x02000000

Length Error

Definition at line 366 of file lpc17xx_emac.h.

#define EMAC_RINFO_MCAST   0x00200000

Multicast Frame

Definition at line 362 of file lpc17xx_emac.h.

#define EMAC_RINFO_NO_DESCR   0x20000000

No new Descriptor available

Definition at line 370 of file lpc17xx_emac.h.

#define EMAC_RINFO_OVERRUN   0x10000000

Receive overrun

Definition at line 369 of file lpc17xx_emac.h.

#define EMAC_RINFO_RANGE_ERR   0x04000000

Range Error (exceeded max. size)

Definition at line 367 of file lpc17xx_emac.h.

#define EMAC_RINFO_SIZE   0x000007FF

Macro defines for RX Status Information WordData size in bytes

Definition at line 358 of file lpc17xx_emac.h.

#define EMAC_RINFO_SYM_ERR   0x01000000

Symbol Error from PHY

Definition at line 365 of file lpc17xx_emac.h.

#define EMAC_RINFO_VLAN   0x00080000

VLAN Frame

Definition at line 360 of file lpc17xx_emac.h.

#define EMAC_RSV_BCAST   0x02000000

Broadcast Frame

Definition at line 276 of file lpc17xx_emac.h.

#define EMAC_RSV_BYTE_CNT   0x0000FFFF

Macro defines for Receive Status Vector RegisterReceive Byte Count

Definition at line 266 of file lpc17xx_emac.h.

#define EMAC_RSV_CARR_SEEN   0x00040000

Carrier Event Previously Seen

Definition at line 269 of file lpc17xx_emac.h.

#define EMAC_RSV_CRC_ERR   0x00100000

CRC Error

Definition at line 271 of file lpc17xx_emac.h.

#define EMAC_RSV_CTRL_FRAME   0x08000000

Control Frame

Definition at line 278 of file lpc17xx_emac.h.

#define EMAC_RSV_DRIB_NIBB   0x04000000

Dribble Nibble

Definition at line 277 of file lpc17xx_emac.h.

#define EMAC_RSV_LEN_CHKERR   0x00200000

Length Check Error

Definition at line 272 of file lpc17xx_emac.h.

#define EMAC_RSV_LEN_OUTRNG   0x00400000

Length Out of Range

Definition at line 273 of file lpc17xx_emac.h.

#define EMAC_RSV_MCAST   0x01000000

Multicast Frame

Definition at line 275 of file lpc17xx_emac.h.

#define EMAC_RSV_PAUSE   0x10000000

Pause Frame

Definition at line 279 of file lpc17xx_emac.h.

#define EMAC_RSV_PKT_IGNORED   0x00010000

Packet Previously Ignored

Definition at line 267 of file lpc17xx_emac.h.

#define EMAC_RSV_REC_CODEV   0x00080000

Receive Code Violation

Definition at line 270 of file lpc17xx_emac.h.

#define EMAC_RSV_REC_OK   0x00800000

Frame Received OK

Definition at line 274 of file lpc17xx_emac.h.

#define EMAC_RSV_RXDV_SEEN   0x00020000

RXDV Event Previously Seen

Definition at line 268 of file lpc17xx_emac.h.

#define EMAC_RSV_UNSUPP_OPC   0x20000000

Unsupported Opcode

Definition at line 280 of file lpc17xx_emac.h.

#define EMAC_RSV_VLAN   0x40000000

VLAN Frame

Definition at line 281 of file lpc17xx_emac.h.

#define EMAC_SR_RX_EN   0x00000001

Macro defines for Status RegisterEnable Receive

Definition at line 233 of file lpc17xx_emac.h.

#define EMAC_SR_TX_EN   0x00000002

Enable Transmit

Definition at line 234 of file lpc17xx_emac.h.

#define EMAC_SUPP_RES_RMII   0x00000800

Reset Reduced MII Logic

Definition at line 159 of file lpc17xx_emac.h.

#define EMAC_SUPP_SPEED   0x00000100

Macro defines for PHY Support RegisterReduced MII Logic Current Speed

Definition at line 158 of file lpc17xx_emac.h.

#define EMAC_TCTRL_CRC   0x20000000

Append a hardware CRC to Frame

Definition at line 383 of file lpc17xx_emac.h.

#define EMAC_TCTRL_HUGE   0x08000000

Enable Huge Frame

Definition at line 381 of file lpc17xx_emac.h.

#define EMAC_TCTRL_INT   0x80000000

Generate TxDone Interrupt

Definition at line 385 of file lpc17xx_emac.h.

#define EMAC_TCTRL_LAST   0x40000000

Last Descriptor for TX Frame

Definition at line 384 of file lpc17xx_emac.h.

#define EMAC_TCTRL_OVERRIDE   0x04000000

Override Default MAC Registers

Definition at line 380 of file lpc17xx_emac.h.

#define EMAC_TCTRL_PAD   0x10000000

Pad short Frames to 64 bytes

Definition at line 382 of file lpc17xx_emac.h.

#define EMAC_TCTRL_SIZE   0x000007FF

Macro defines for TX Descriptor Control WordSize of data buffer in bytes

Definition at line 379 of file lpc17xx_emac.h.

#define EMAC_TEST_SHCUT_PQUANTA   0x00000001

Macro defines for Test RegisterShortcut Pause Quanta

Definition at line 164 of file lpc17xx_emac.h.

#define EMAC_TEST_TST_BACKP   0x00000004

Test Back Pressure

Definition at line 166 of file lpc17xx_emac.h.

#define EMAC_TEST_TST_PAUSE   0x00000002

Test Pause

Definition at line 165 of file lpc17xx_emac.h.

#define EMAC_TINFO_COL_CNT   0x01E00000

Macro defines for TX Status Information WordCollision Count

Definition at line 390 of file lpc17xx_emac.h.

#define EMAC_TINFO_DEFER   0x02000000

Packet Deferred (not an error)

Definition at line 391 of file lpc17xx_emac.h.

#define EMAC_TINFO_ERR   0x80000000

Error Occured (OR of all errors)

Definition at line 397 of file lpc17xx_emac.h.

#define EMAC_TINFO_EXCESS_COL   0x08000000

Excessive Collision

Definition at line 393 of file lpc17xx_emac.h.

#define EMAC_TINFO_EXCESS_DEF   0x04000000

Excessive Deferral

Definition at line 392 of file lpc17xx_emac.h.

#define EMAC_TINFO_LATE_COL   0x10000000

Late Collision Occured

Definition at line 394 of file lpc17xx_emac.h.

#define EMAC_TINFO_NO_DESCR   0x40000000

No new Descriptor available

Definition at line 396 of file lpc17xx_emac.h.

#define EMAC_TINFO_UNDERRUN   0x20000000

Transmit Underrun

Definition at line 395 of file lpc17xx_emac.h.

#define EMAC_TSV0_BACK_PRESS   0x40000000

Backpressure Method Applied

Definition at line 254 of file lpc17xx_emac.h.

#define EMAC_TSV0_BCAST   0x00000020

Broadcast Destination

Definition at line 244 of file lpc17xx_emac.h.

#define EMAC_TSV0_BYTES   0x0FFFF000

Total Bytes Transferred

Definition at line 251 of file lpc17xx_emac.h.

#define EMAC_TSV0_CRC_ERR   0x00000001

Macro defines for Transmit Status Vector 0 RegisterCRC error

Definition at line 239 of file lpc17xx_emac.h.

#define EMAC_TSV0_CTRL_FRAME   0x10000000

Control Frame

Definition at line 252 of file lpc17xx_emac.h.

#define EMAC_TSV0_DONE   0x00000008

Tramsmission Completed

Definition at line 242 of file lpc17xx_emac.h.

#define EMAC_TSV0_EXC_COLL   0x00000100

Excessive Collision

Definition at line 247 of file lpc17xx_emac.h.

#define EMAC_TSV0_EXC_DEFER   0x00000080

Excessive Packet Deferral

Definition at line 246 of file lpc17xx_emac.h.

#define EMAC_TSV0_GIANT   0x00000400

Giant Frame

Definition at line 249 of file lpc17xx_emac.h.

#define EMAC_TSV0_LATE_COLL   0x00000200

Late Collision Occured

Definition at line 248 of file lpc17xx_emac.h.

#define EMAC_TSV0_LEN_CHKERR   0x00000002

Length Check Error

Definition at line 240 of file lpc17xx_emac.h.

#define EMAC_TSV0_LEN_OUTRNG   0x00000004

Length Out of Range

Definition at line 241 of file lpc17xx_emac.h.

#define EMAC_TSV0_MCAST   0x00000010

Multicast Destination

Definition at line 243 of file lpc17xx_emac.h.

#define EMAC_TSV0_PAUSE   0x20000000

Pause Frame

Definition at line 253 of file lpc17xx_emac.h.

#define EMAC_TSV0_PKT_DEFER   0x00000040

Packet Deferred

Definition at line 245 of file lpc17xx_emac.h.

#define EMAC_TSV0_UNDERRUN   0x00000800

Buffer Underrun

Definition at line 250 of file lpc17xx_emac.h.

#define EMAC_TSV0_VLAN   0x80000000

VLAN Frame

Definition at line 255 of file lpc17xx_emac.h.

#define EMAC_TSV1_BYTE_CNT   0x0000FFFF

Macro defines for Transmit Status Vector 1 RegisterTransmit Byte Count

Definition at line 260 of file lpc17xx_emac.h.

#define EMAC_TSV1_COLL_CNT   0x000F0000

Transmit Collision Count

Definition at line 261 of file lpc17xx_emac.h.

#define EMAC_TX_FRAME_TOUT   0x00100000

Frame Transmit timeout count

Definition at line 74 of file lpc17xx_emac.h.

#define EMAC_WOL_BCAST   0x00000002

Broadcast Frame caused WoL

Definition at line 312 of file lpc17xx_emac.h.

#define EMAC_WOL_BITMASK   0x01BF

Receive Filter WoL Status/Clear bitmasl value

Definition at line 319 of file lpc17xx_emac.h.

#define EMAC_WOL_MAG_PACKET   0x00000100

Magic Packet Filter caused WoL

Definition at line 318 of file lpc17xx_emac.h.

#define EMAC_WOL_MCAST   0x00000004

Multicast Frame caused WoL

Definition at line 313 of file lpc17xx_emac.h.

#define EMAC_WOL_MCAST_HASH   0x00000010

Multicast Hash Filter Frame WoL

Definition at line 315 of file lpc17xx_emac.h.

#define EMAC_WOL_PERFECT   0x00000020

Perfect Filter WoL

Definition at line 316 of file lpc17xx_emac.h.

#define EMAC_WOL_RX_FILTER   0x00000080

RX Filter caused WoL

Definition at line 317 of file lpc17xx_emac.h.

#define EMAC_WOL_UCAST   0x00000001

Macro defines for Receive Filter WoL Status/Clear RegistersUnicast Frame caused WoL

Definition at line 311 of file lpc17xx_emac.h.

#define EMAC_WOL_UCAST_HASH   0x00000008

Unicast Hash Filter Frame WoL

Definition at line 314 of file lpc17xx_emac.h.