lpc17xx_emac.h

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/***********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
#ifndef LPC17XX_EMAC_H_
#define LPC17XX_EMAC_H_

/* Includes ------------------------------------------------------------------- */
#include "LPC17xx.h"
#include "lpc_types.h"


#ifdef __cplusplus
extern "C"
{
#endif

#define MCB_LPC_1768
//#define IAR_LPC_1768

/* Public Macros -------------------------------------------------------------- */
/* EMAC PHY status type definitions */
#define EMAC_PHY_STAT_LINK          (0)     
#define EMAC_PHY_STAT_SPEED         (1)     
#define EMAC_PHY_STAT_DUP           (2)     
/* EMAC PHY device Speed definitions */
#define EMAC_MODE_AUTO              (0)     
#define EMAC_MODE_10M_FULL          (1)     
#define EMAC_MODE_10M_HALF          (2)     
#define EMAC_MODE_100M_FULL         (3)     
#define EMAC_MODE_100M_HALF         (4)     
/* Private Macros ------------------------------------------------------------- */

/* EMAC Memory Buffer configuration for 16K Ethernet RAM */
#define EMAC_NUM_RX_FRAG         4           
#define EMAC_NUM_TX_FRAG         3           
#define EMAC_ETH_MAX_FLEN        1536        
#define EMAC_TX_FRAME_TOUT       0x00100000  
/* --------------------- BIT DEFINITIONS -------------------------------------- */
/*********************************************************************/
#define EMAC_MAC1_REC_EN         0x00000001  
#define EMAC_MAC1_PASS_ALL       0x00000002  
#define EMAC_MAC1_RX_FLOWC       0x00000004  
#define EMAC_MAC1_TX_FLOWC       0x00000008  
#define EMAC_MAC1_LOOPB          0x00000010  
#define EMAC_MAC1_RES_TX         0x00000100  
#define EMAC_MAC1_RES_MCS_TX     0x00000200  
#define EMAC_MAC1_RES_RX         0x00000400  
#define EMAC_MAC1_RES_MCS_RX     0x00000800  
#define EMAC_MAC1_SIM_RES        0x00004000  
#define EMAC_MAC1_SOFT_RES       0x00008000  
/*********************************************************************/
#define EMAC_MAC2_FULL_DUP       0x00000001  
#define EMAC_MAC2_FRM_LEN_CHK    0x00000002  
#define EMAC_MAC2_HUGE_FRM_EN    0x00000004  
#define EMAC_MAC2_DLY_CRC        0x00000008  
#define EMAC_MAC2_CRC_EN         0x00000010  
#define EMAC_MAC2_PAD_EN         0x00000020  
#define EMAC_MAC2_VLAN_PAD_EN    0x00000040  
#define EMAC_MAC2_ADET_PAD_EN    0x00000080  
#define EMAC_MAC2_PPREAM_ENF     0x00000100  
#define EMAC_MAC2_LPREAM_ENF     0x00000200  
#define EMAC_MAC2_NO_BACKOFF     0x00001000  
#define EMAC_MAC2_BACK_PRESSURE  0x00002000  
#define EMAC_MAC2_EXCESS_DEF     0x00004000  
/*********************************************************************/
#define EMAC_IPGT_BBIPG(n)      (n&0x7F)

#define EMAC_IPGT_FULL_DUP      (EMAC_IPGT_BBIPG(0x15))

#define EMAC_IPGT_HALF_DUP      (EMAC_IPGT_BBIPG(0x12))

/*********************************************************************/
#define EMAC_IPGR_NBBIPG_P2(n)  (n&0x7F)

#define EMAC_IPGR_P2_DEF        (EMAC_IPGR_NBBIPG_P2(0x12))

#define EMAC_IPGR_NBBIPG_P1(n)  ((n&0x7F)<<8)

#define EMAC_IPGR_P1_DEF        EMAC_IPGR_NBBIPG_P1(0x0C)

/*********************************************************************/
#define EMAC_CLRT_MAX_RETX(n)   (n&0x0F)

#define EMAC_CLRT_COLL(n)       ((n&0x3F)<<8)

#define EMAC_CLRT_DEF           ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))

/*********************************************************************/
#define EMAC_MAXF_MAXFRMLEN(n)  (n&0xFFFF)

/*********************************************************************/
#define EMAC_SUPP_SPEED         0x00000100      
#define EMAC_SUPP_RES_RMII      0x00000800      
/*********************************************************************/
#define EMAC_TEST_SHCUT_PQUANTA  0x00000001     
#define EMAC_TEST_TST_PAUSE      0x00000002     
#define EMAC_TEST_TST_BACKP      0x00000004     
/*********************************************************************/
#define EMAC_MCFG_SCAN_INC       0x00000001     
#define EMAC_MCFG_SUPP_PREAM     0x00000002     
#define EMAC_MCFG_CLK_SEL(n)     ((n&0x0F)<<2)  
#define EMAC_MCFG_RES_MII        0x00008000     
#define EMAC_MCFG_MII_MAXCLK     2500000UL      
/*********************************************************************/
#define EMAC_MCMD_READ           0x00000001     
#define EMAC_MCMD_SCAN           0x00000002     
#define EMAC_MII_WR_TOUT         0x00050000     
#define EMAC_MII_RD_TOUT         0x00050000     
/*********************************************************************/
#define EMAC_MADR_REG_ADR(n)     (n&0x1F)       
#define EMAC_MADR_PHY_ADR(n)     ((n&0x1F)<<8)  
/*********************************************************************/
#define EMAC_MWTD_DATA(n)       (n&0xFFFF)      
/*********************************************************************/
#define EMAC_MRDD_DATA(n)       (n&0xFFFF)      
/*********************************************************************/
#define EMAC_MIND_BUSY           0x00000001     
#define EMAC_MIND_SCAN           0x00000002     
#define EMAC_MIND_NOT_VAL        0x00000004     
#define EMAC_MIND_MII_LINK_FAIL  0x00000008     
/* Station Address 0 Register */
/* Station Address 1 Register */
/* Station Address 2 Register */


/* Control register definitions --------------------------------------------------------------------------- */
/*********************************************************************/
#define EMAC_CR_RX_EN            0x00000001     
#define EMAC_CR_TX_EN            0x00000002     
#define EMAC_CR_REG_RES          0x00000008     
#define EMAC_CR_TX_RES           0x00000010     
#define EMAC_CR_RX_RES           0x00000020     
#define EMAC_CR_PASS_RUNT_FRM    0x00000040     
#define EMAC_CR_PASS_RX_FILT     0x00000080     
#define EMAC_CR_TX_FLOW_CTRL     0x00000100     
#define EMAC_CR_RMII             0x00000200     
#define EMAC_CR_FULL_DUP         0x00000400     
/*********************************************************************/
#define EMAC_SR_RX_EN            0x00000001     
#define EMAC_SR_TX_EN            0x00000002     
/*********************************************************************/
#define EMAC_TSV0_CRC_ERR        0x00000001  
#define EMAC_TSV0_LEN_CHKERR     0x00000002  
#define EMAC_TSV0_LEN_OUTRNG     0x00000004  
#define EMAC_TSV0_DONE           0x00000008  
#define EMAC_TSV0_MCAST          0x00000010  
#define EMAC_TSV0_BCAST          0x00000020  
#define EMAC_TSV0_PKT_DEFER      0x00000040  
#define EMAC_TSV0_EXC_DEFER      0x00000080  
#define EMAC_TSV0_EXC_COLL       0x00000100  
#define EMAC_TSV0_LATE_COLL      0x00000200  
#define EMAC_TSV0_GIANT          0x00000400  
#define EMAC_TSV0_UNDERRUN       0x00000800  
#define EMAC_TSV0_BYTES          0x0FFFF000  
#define EMAC_TSV0_CTRL_FRAME     0x10000000  
#define EMAC_TSV0_PAUSE          0x20000000  
#define EMAC_TSV0_BACK_PRESS     0x40000000  
#define EMAC_TSV0_VLAN           0x80000000  
/*********************************************************************/
#define EMAC_TSV1_BYTE_CNT       0x0000FFFF  
#define EMAC_TSV1_COLL_CNT       0x000F0000  
/*********************************************************************/
#define EMAC_RSV_BYTE_CNT        0x0000FFFF  
#define EMAC_RSV_PKT_IGNORED     0x00010000  
#define EMAC_RSV_RXDV_SEEN       0x00020000  
#define EMAC_RSV_CARR_SEEN       0x00040000  
#define EMAC_RSV_REC_CODEV       0x00080000  
#define EMAC_RSV_CRC_ERR         0x00100000  
#define EMAC_RSV_LEN_CHKERR      0x00200000  
#define EMAC_RSV_LEN_OUTRNG      0x00400000  
#define EMAC_RSV_REC_OK          0x00800000  
#define EMAC_RSV_MCAST           0x01000000  
#define EMAC_RSV_BCAST           0x02000000  
#define EMAC_RSV_DRIB_NIBB       0x04000000  
#define EMAC_RSV_CTRL_FRAME      0x08000000  
#define EMAC_RSV_PAUSE           0x10000000  
#define EMAC_RSV_UNSUPP_OPC      0x20000000  
#define EMAC_RSV_VLAN            0x40000000  
/*********************************************************************/
#define EMAC_FCC_MIRR_CNT(n)            (n&0xFFFF)          
#define EMAC_FCC_PAUSE_TIM(n)           ((n&0xFFFF)<<16)    
/*********************************************************************/
#define EMAC_FCS_MIRR_CNT(n)            (n&0xFFFF)          
/* Receive filter register definitions -------------------------------------------------------- */
/*********************************************************************/
#define EMAC_RFC_UCAST_EN        0x00000001  
#define EMAC_RFC_BCAST_EN        0x00000002  
#define EMAC_RFC_MCAST_EN        0x00000004  
#define EMAC_RFC_UCAST_HASH_EN   0x00000008  
#define EMAC_RFC_MCAST_HASH_EN   0x00000010  
#define EMAC_RFC_PERFECT_EN      0x00000020  
#define EMAC_RFC_MAGP_WOL_EN     0x00001000  
#define EMAC_RFC_PFILT_WOL_EN    0x00002000  
/*********************************************************************/
#define EMAC_WOL_UCAST           0x00000001  
#define EMAC_WOL_BCAST           0x00000002  
#define EMAC_WOL_MCAST           0x00000004  
#define EMAC_WOL_UCAST_HASH      0x00000008  
#define EMAC_WOL_MCAST_HASH      0x00000010  
#define EMAC_WOL_PERFECT         0x00000020  
#define EMAC_WOL_RX_FILTER       0x00000080  
#define EMAC_WOL_MAG_PACKET      0x00000100  
#define EMAC_WOL_BITMASK         0x01BF     
/* Module control register definitions ---------------------------------------------------- */
/*********************************************************************/
#define EMAC_INT_RX_OVERRUN      0x00000001  
#define EMAC_INT_RX_ERR          0x00000002  
#define EMAC_INT_RX_FIN          0x00000004  
#define EMAC_INT_RX_DONE         0x00000008  
#define EMAC_INT_TX_UNDERRUN     0x00000010  
#define EMAC_INT_TX_ERR          0x00000020  
#define EMAC_INT_TX_FIN          0x00000040  
#define EMAC_INT_TX_DONE         0x00000080  
#define EMAC_INT_SOFT_INT        0x00001000  
#define EMAC_INT_WAKEUP          0x00002000  
/*********************************************************************/
#define EMAC_PD_POWER_DOWN       0x80000000  
/* Descriptor and status formats ---------------------------------------------------- */
/*********************************************************************/
#define EMAC_RCTRL_SIZE(n)       (n&0x7FF)      
#define EMAC_RCTRL_INT           0x80000000     
/*********************************************************************/
#define EMAC_RHASH_SA            0x000001FF     
#define EMAC_RHASH_DA            0x001FF000     
/*********************************************************************/
#define EMAC_RINFO_SIZE          0x000007FF  
#define EMAC_RINFO_CTRL_FRAME    0x00040000  
#define EMAC_RINFO_VLAN          0x00080000  
#define EMAC_RINFO_FAIL_FILT     0x00100000  
#define EMAC_RINFO_MCAST         0x00200000  
#define EMAC_RINFO_BCAST         0x00400000  
#define EMAC_RINFO_CRC_ERR       0x00800000  
#define EMAC_RINFO_SYM_ERR       0x01000000  
#define EMAC_RINFO_LEN_ERR       0x02000000  
#define EMAC_RINFO_RANGE_ERR     0x04000000  
#define EMAC_RINFO_ALIGN_ERR     0x08000000  
#define EMAC_RINFO_OVERRUN       0x10000000  
#define EMAC_RINFO_NO_DESCR      0x20000000  
#define EMAC_RINFO_LAST_FLAG     0x40000000  
#define EMAC_RINFO_ERR           0x80000000  
#define EMAC_RINFO_ERR_MASK     (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR   | EMAC_RINFO_SYM_ERR | \
EMAC_RINFO_LEN_ERR   | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)

/*********************************************************************/
#define EMAC_TCTRL_SIZE          0x000007FF  
#define EMAC_TCTRL_OVERRIDE      0x04000000  
#define EMAC_TCTRL_HUGE          0x08000000  
#define EMAC_TCTRL_PAD           0x10000000  
#define EMAC_TCTRL_CRC           0x20000000  
#define EMAC_TCTRL_LAST          0x40000000  
#define EMAC_TCTRL_INT           0x80000000  
/*********************************************************************/
#define EMAC_TINFO_COL_CNT       0x01E00000  
#define EMAC_TINFO_DEFER         0x02000000  
#define EMAC_TINFO_EXCESS_DEF    0x04000000  
#define EMAC_TINFO_EXCESS_COL    0x08000000  
#define EMAC_TINFO_LATE_COL      0x10000000  
#define EMAC_TINFO_UNDERRUN      0x20000000  
#define EMAC_TINFO_NO_DESCR      0x40000000  
#define EMAC_TINFO_ERR           0x80000000  
#ifdef MCB_LPC_1768
/* DP83848C PHY definition ------------------------------------------------------------ */

#define EMAC_PHY_RESP_TOUT      0x100000UL

/* ENET Device Revision ID */
#define EMAC_OLD_EMAC_MODULE_ID  0x39022000  
/*********************************************************************/
#define EMAC_PHY_REG_BMCR        0x00        
#define EMAC_PHY_REG_BMSR        0x01        
#define EMAC_PHY_REG_IDR1        0x02        
#define EMAC_PHY_REG_IDR2        0x03        
#define EMAC_PHY_REG_ANAR        0x04        
#define EMAC_PHY_REG_ANLPAR      0x05        
#define EMAC_PHY_REG_ANER        0x06        
#define EMAC_PHY_REG_ANNPTR      0x07        
#define EMAC_PHY_REG_LPNPA       0x08

/*********************************************************************/
#define EMAC_PHY_REG_STS         0x10        
#define EMAC_PHY_REG_MICR        0x11        
#define EMAC_PHY_REG_MISR        0x12        
#define EMAC_PHY_REG_FCSCR       0x14        
#define EMAC_PHY_REG_RECR        0x15        
#define EMAC_PHY_REG_PCSR        0x16        
#define EMAC_PHY_REG_RBR         0x17        
#define EMAC_PHY_REG_LEDCR       0x18        
#define EMAC_PHY_REG_PHYCR       0x19        
#define EMAC_PHY_REG_10BTSCR     0x1A        
#define EMAC_PHY_REG_CDCTRL1     0x1B        
#define EMAC_PHY_REG_EDCR        0x1D        
/*********************************************************************/
#define EMAC_PHY_BMCR_RESET                 (1<<15)     
#define EMAC_PHY_BMCR_LOOPBACK              (1<<14)     
#define EMAC_PHY_BMCR_SPEED_SEL             (1<<13)     
#define EMAC_PHY_BMCR_AN                    (1<<12)     
#define EMAC_PHY_BMCR_POWERDOWN             (1<<11)     
#define EMAC_PHY_BMCR_ISOLATE               (1<<10)     
#define EMAC_PHY_BMCR_RE_AN                 (1<<9)      
#define EMAC_PHY_BMCR_DUPLEX                (1<<8)      
/*********************************************************************/
#define EMAC_PHY_BMSR_100BE_T4              (1<<15)     
#define EMAC_PHY_BMSR_100TX_FULL            (1<<14)     
#define EMAC_PHY_BMSR_100TX_HALF            (1<<13)     
#define EMAC_PHY_BMSR_10BE_FULL             (1<<12)     
#define EMAC_PHY_BMSR_10BE_HALF             (1<<11)     
#define EMAC_PHY_BMSR_NOPREAM               (1<<6)      
#define EMAC_PHY_BMSR_AUTO_DONE             (1<<5)      
#define EMAC_PHY_BMSR_REMOTE_FAULT          (1<<4)      
#define EMAC_PHY_BMSR_NO_AUTO               (1<<3)      
#define EMAC_PHY_BMSR_LINK_ESTABLISHED      (1<<2)      
/*********************************************************************/
#define EMAC_PHY_SR_REMOTE_FAULT            (1<<6)      
#define EMAC_PHY_SR_JABBER                  (1<<5)      
#define EMAC_PHY_SR_AUTO_DONE               (1<<4)      
#define EMAC_PHY_SR_LOOPBACK                (1<<3)      
#define EMAC_PHY_SR_DUP                     (1<<2)      
#define EMAC_PHY_SR_SPEED                   (1<<1)      
#define EMAC_PHY_SR_LINK                    (1<<0)      
#define EMAC_PHY_FULLD_100M      0x2100      
#define EMAC_PHY_HALFD_100M      0x2000      
#define EMAC_PHY_FULLD_10M       0x0100      
#define EMAC_PHY_HALFD_10M       0x0000      
#define EMAC_PHY_AUTO_NEG        0x3000      
#define EMAC_DEF_ADR    0x0100      
#define EMAC_DP83848C_ID         0x20005C90  
#define EMAC_PHY_SR_100_SPEED       ((1<<14)|(1<<13))
#define EMAC_PHY_SR_FULL_DUP        ((1<<14)|(1<<12))
#define EMAC_PHY_BMSR_LINK_STATUS           (1<<2)      
#elif defined(IAR_LPC_1768)
/* KSZ8721BL PHY definition ------------------------------------------------------------ */
#define EMAC_PHY_RESP_TOUT      0x100000UL

/* ENET Device Revision ID */
#define EMAC_OLD_EMAC_MODULE_ID  0x39022000  
/*********************************************************************/
#define EMAC_PHY_REG_BMCR        0x00        
#define EMAC_PHY_REG_BMSR        0x01        
#define EMAC_PHY_REG_IDR1        0x02        
#define EMAC_PHY_REG_IDR2        0x03        
#define EMAC_PHY_REG_ANAR        0x04        
#define EMAC_PHY_REG_ANLPAR      0x05        
#define EMAC_PHY_REG_ANER        0x06        
#define EMAC_PHY_REG_ANNPTR      0x07        
#define EMAC_PHY_REG_LPNPA       0x08        
#define EMAC_PHY_REG_REC         0x15        
#define EMAC_PHY_REG_ISC         0x1b        
#define EMAC_PHY_REG_100BASE     0x1f        
/*********************************************************************/
#define EMAC_PHY_BMCR_RESET                 (1<<15)     
#define EMAC_PHY_BMCR_LOOPBACK              (1<<14)     
#define EMAC_PHY_BMCR_SPEED_SEL             (1<<13)     
#define EMAC_PHY_BMCR_AN                    (1<<12)     
#define EMAC_PHY_BMCR_POWERDOWN             (1<<11)     
#define EMAC_PHY_BMCR_ISOLATE               (1<<10)     
#define EMAC_PHY_BMCR_RE_AN                 (1<<9)      
#define EMAC_PHY_BMCR_DUPLEX                (1<<8)      
#define EMAC_PHY_BMCR_COLLISION             (1<<7)      
#define EMAC_PHY_BMCR_TXDIS                 (1<<0)      
/*********************************************************************/
#define EMAC_PHY_BMSR_100BE_T4              (1<<15)     
#define EMAC_PHY_BMSR_100TX_FULL            (1<<14)     
#define EMAC_PHY_BMSR_100TX_HALF            (1<<13)     
#define EMAC_PHY_BMSR_10BE_FULL             (1<<12)     
#define EMAC_PHY_BMSR_10BE_HALF             (1<<11)     
#define EMAC_PHY_BMSR_NOPREAM               (1<<6)      
#define EMAC_PHY_BMSR_AUTO_DONE             (1<<5)      
#define EMAC_PHY_BMSR_REMOTE_FAULT          (1<<4)      
#define EMAC_PHY_BMSR_NO_AUTO               (1<<3)      
#define EMAC_PHY_BMSR_LINK_STATUS           (1<<2)      
#define EMAC_PHY_BMSR_JABBER_DETECT         (1<<1)      
#define EMAC_PHY_BMSR_EXTEND                (1<<0)      
/*********************************************************************/
/* PHY Identifier 1 bitmap definitions */
#define EMAC_PHY_IDR1(n)        (n & 0xFFFF)        
/* PHY Identifier 2 bitmap definitions */
#define EMAC_PHY_IDR2(n)        (n & 0xFFFF)        
/*********************************************************************/
#define EMAC_PHY_AN_NEXTPAGE                    (1<<15)     
#define EMAC_PHY_AN_REMOTE_FAULT                (1<<13)     
#define EMAC_PHY_AN_PAUSE                       (1<<10)     
#define EMAC_PHY_AN_100BASE_T4                  (1<<9)      
#define EMAC_PHY_AN_100BASE_TX_FD               (1<<8)      
#define EMAC_PHY_AN_100BASE_TX                  (1<<7)      
#define EMAC_PHY_AN_10BASE_T_FD                 (1<<6)      
#define EMAC_PHY_AN_10BASE_T                    (1<<5)      
#define EMAC_PHY_AN_FIELD(n)                    (n & 0x1F)  
#define EMAC_PHY_FULLD_100M      0x2100      
#define EMAC_PHY_HALFD_100M      0x2000      
#define EMAC_PHY_FULLD_10M       0x0100      
#define EMAC_PHY_HALFD_10M       0x0000      
#define EMAC_PHY_AUTO_NEG        0x3000      
#define EMAC_PHY_SR_100_SPEED       ((1<<14)|(1<<13))
#define EMAC_PHY_SR_FULL_DUP        ((1<<14)|(1<<12))

#define EMAC_DEF_ADR    (0x01<<8)       
#define EMAC_KSZ8721BL_ID   ((0x22 << 16) | 0x1619 ) 
#endif

/* Public Types --------------------------------------------------------------- */
/* Descriptor and status formats ---------------------------------------------- */

typedef struct {
    uint32_t Packet;    
    uint32_t Ctrl;      
} RX_Desc;

typedef struct {
    uint32_t Info;      
    uint32_t HashCRC;   
} RX_Stat;

typedef struct {
    uint32_t Packet;    
    uint32_t Ctrl;      
} TX_Desc;

typedef struct {
   uint32_t Info;       
} TX_Stat;


typedef struct {
    uint32_t ulDataLen;         
    uint32_t *pbDataBuf;        
} EMAC_PACKETBUF_Type;

typedef struct {
    uint32_t    Mode;                       
    uint8_t     *pbEMAC_Addr;               
} EMAC_CFG_Type;


/* Public Functions ----------------------------------------------------------- */
/* Init/DeInit EMAC peripheral */
Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct);
void EMAC_DeInit(void);

/* PHY functions --------------*/
int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState);
int32_t EMAC_SetPHYMode(uint32_t ulPHYMode);
int32_t EMAC_UpdatePHYStatus(void);

/* Filter functions ----------*/
void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState);
void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState);

/* EMAC Packet Buffer functions */
void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct, Bool Finalize);
void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct);

/* EMAC Interrupt functions -------*/
void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState);
IntStatus EMAC_IntGetStatus(uint32_t ulIntType);

/* EMAC Index functions -----------*/
Bool EMAC_CheckReceiveIndex(void);
Bool EMAC_CheckTransmitIndex(void);
void EMAC_UpdateRxConsumeIndex(void);
void EMAC_UpdateTxProduceIndex(void);

FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType);
uint32_t EMAC_GetReceiveDataSize(void);
FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode);

#ifdef __cplusplus
}
#endif

#endif /* LPC17XX_EMAC_H_ */

/* --------------------------------- End Of File ------------------------------ */