uc-sdk
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This file contains all the functions prototypes for the RCC firmware library. More...
#include "stm32f10x.h"
Go to the source code of this file.
Classes | |
struct | RCC_ClocksTypeDef |
Macros | |
#define | RCC_HSE_OFF ((uint32_t)0x00000000) |
#define | RCC_HSE_ON ((uint32_t)0x00010000) |
#define | RCC_HSE_Bypass ((uint32_t)0x00040000) |
#define | IS_RCC_HSE(HSE) |
#define | RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) |
#define | RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) |
#define | RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) |
#define | IS_RCC_PLL_SOURCE(SOURCE) |
#define | RCC_PLLMul_2 ((uint32_t)0x00000000) |
#define | RCC_PLLMul_3 ((uint32_t)0x00040000) |
#define | RCC_PLLMul_4 ((uint32_t)0x00080000) |
#define | RCC_PLLMul_5 ((uint32_t)0x000C0000) |
#define | RCC_PLLMul_6 ((uint32_t)0x00100000) |
#define | RCC_PLLMul_7 ((uint32_t)0x00140000) |
#define | RCC_PLLMul_8 ((uint32_t)0x00180000) |
#define | RCC_PLLMul_9 ((uint32_t)0x001C0000) |
#define | RCC_PLLMul_10 ((uint32_t)0x00200000) |
#define | RCC_PLLMul_11 ((uint32_t)0x00240000) |
#define | RCC_PLLMul_12 ((uint32_t)0x00280000) |
#define | RCC_PLLMul_13 ((uint32_t)0x002C0000) |
#define | RCC_PLLMul_14 ((uint32_t)0x00300000) |
#define | RCC_PLLMul_15 ((uint32_t)0x00340000) |
#define | RCC_PLLMul_16 ((uint32_t)0x00380000) |
#define | IS_RCC_PLL_MUL(MUL) |
#define | RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) |
#define | RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) |
#define | RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) |
#define | IS_RCC_SYSCLK_SOURCE(SOURCE) |
#define | RCC_SYSCLK_Div1 ((uint32_t)0x00000000) |
#define | RCC_SYSCLK_Div2 ((uint32_t)0x00000080) |
#define | RCC_SYSCLK_Div4 ((uint32_t)0x00000090) |
#define | RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) |
#define | RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) |
#define | RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) |
#define | RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) |
#define | RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) |
#define | RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) |
#define | IS_RCC_HCLK(HCLK) |
#define | RCC_HCLK_Div1 ((uint32_t)0x00000000) |
#define | RCC_HCLK_Div2 ((uint32_t)0x00000400) |
#define | RCC_HCLK_Div4 ((uint32_t)0x00000500) |
#define | RCC_HCLK_Div8 ((uint32_t)0x00000600) |
#define | RCC_HCLK_Div16 ((uint32_t)0x00000700) |
#define | IS_RCC_PCLK(PCLK) |
#define | RCC_IT_LSIRDY ((uint8_t)0x01) |
#define | RCC_IT_LSERDY ((uint8_t)0x02) |
#define | RCC_IT_HSIRDY ((uint8_t)0x04) |
#define | RCC_IT_HSERDY ((uint8_t)0x08) |
#define | RCC_IT_PLLRDY ((uint8_t)0x10) |
#define | RCC_IT_CSS ((uint8_t)0x80) |
#define | IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) |
#define | IS_RCC_GET_IT(IT) |
#define | IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) |
#define | RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) |
#define | RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) |
#define | IS_RCC_USBCLK_SOURCE(SOURCE) |
#define | RCC_PCLK2_Div2 ((uint32_t)0x00000000) |
#define | RCC_PCLK2_Div4 ((uint32_t)0x00004000) |
#define | RCC_PCLK2_Div6 ((uint32_t)0x00008000) |
#define | RCC_PCLK2_Div8 ((uint32_t)0x0000C000) |
#define | IS_RCC_ADCCLK(ADCCLK) |
#define | RCC_LSE_OFF ((uint8_t)0x00) |
#define | RCC_LSE_ON ((uint8_t)0x01) |
#define | RCC_LSE_Bypass ((uint8_t)0x04) |
#define | IS_RCC_LSE(LSE) |
#define | RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) |
#define | RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) |
#define | RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) |
#define | IS_RCC_RTCCLK_SOURCE(SOURCE) |
#define | RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) |
#define | RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) |
#define | RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) |
#define | RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) |
#define | RCC_AHBPeriph_CRC ((uint32_t)0x00000040) |
#define | RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) |
#define | RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) |
#define | IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) |
#define | RCC_APB2Periph_AFIO ((uint32_t)0x00000001) |
#define | RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) |
#define | RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) |
#define | RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) |
#define | RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) |
#define | RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) |
#define | RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) |
#define | RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) |
#define | RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) |
#define | RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) |
#define | RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) |
#define | RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) |
#define | RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) |
#define | RCC_APB2Periph_USART1 ((uint32_t)0x00004000) |
#define | RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) |
#define | RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) |
#define | RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) |
#define | RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) |
#define | RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) |
#define | RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) |
#define | RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) |
#define | IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) |
#define | RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) |
#define | RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) |
#define | RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) |
#define | RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) |
#define | RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) |
#define | RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) |
#define | RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) |
#define | RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) |
#define | RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) |
#define | RCC_APB1Periph_WWDG ((uint32_t)0x00000800) |
#define | RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) |
#define | RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) |
#define | RCC_APB1Periph_USART2 ((uint32_t)0x00020000) |
#define | RCC_APB1Periph_USART3 ((uint32_t)0x00040000) |
#define | RCC_APB1Periph_UART4 ((uint32_t)0x00080000) |
#define | RCC_APB1Periph_UART5 ((uint32_t)0x00100000) |
#define | RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) |
#define | RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) |
#define | RCC_APB1Periph_USB ((uint32_t)0x00800000) |
#define | RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) |
#define | RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) |
#define | RCC_APB1Periph_BKP ((uint32_t)0x08000000) |
#define | RCC_APB1Periph_PWR ((uint32_t)0x10000000) |
#define | RCC_APB1Periph_DAC ((uint32_t)0x20000000) |
#define | RCC_APB1Periph_CEC ((uint32_t)0x40000000) |
#define | IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) |
#define | RCC_MCO_NoClock ((uint8_t)0x00) |
#define | RCC_MCO_SYSCLK ((uint8_t)0x04) |
#define | RCC_MCO_HSI ((uint8_t)0x05) |
#define | RCC_MCO_HSE ((uint8_t)0x06) |
#define | RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) |
#define | IS_RCC_MCO(MCO) |
#define | RCC_FLAG_HSIRDY ((uint8_t)0x21) |
#define | RCC_FLAG_HSERDY ((uint8_t)0x31) |
#define | RCC_FLAG_PLLRDY ((uint8_t)0x39) |
#define | RCC_FLAG_LSERDY ((uint8_t)0x41) |
#define | RCC_FLAG_LSIRDY ((uint8_t)0x61) |
#define | RCC_FLAG_PINRST ((uint8_t)0x7A) |
#define | RCC_FLAG_PORRST ((uint8_t)0x7B) |
#define | RCC_FLAG_SFTRST ((uint8_t)0x7C) |
#define | RCC_FLAG_IWDGRST ((uint8_t)0x7D) |
#define | RCC_FLAG_WWDGRST ((uint8_t)0x7E) |
#define | RCC_FLAG_LPWRRST ((uint8_t)0x7F) |
#define | IS_RCC_FLAG(FLAG) |
#define | IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) |
Functions | |
void | RCC_DeInit (void) |
Resets the RCC clock configuration to the default reset state. More... | |
void | RCC_HSEConfig (uint32_t RCC_HSE) |
Configures the External High Speed oscillator (HSE). More... | |
ErrorStatus | RCC_WaitForHSEStartUp (void) |
Waits for HSE start-up. More... | |
void | RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue) |
Adjusts the Internal High Speed oscillator (HSI) calibration value. More... | |
void | RCC_HSICmd (FunctionalState NewState) |
Enables or disables the Internal High Speed oscillator (HSI). More... | |
void | RCC_PLLConfig (uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) |
Configures the PLL clock source and multiplication factor. More... | |
void | RCC_PLLCmd (FunctionalState NewState) |
Enables or disables the PLL. More... | |
void | RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource) |
Configures the system clock (SYSCLK). More... | |
uint8_t | RCC_GetSYSCLKSource (void) |
Returns the clock source used as system clock. More... | |
void | RCC_HCLKConfig (uint32_t RCC_SYSCLK) |
Configures the AHB clock (HCLK). More... | |
void | RCC_PCLK1Config (uint32_t RCC_HCLK) |
Configures the Low Speed APB clock (PCLK1). More... | |
void | RCC_PCLK2Config (uint32_t RCC_HCLK) |
Configures the High Speed APB clock (PCLK2). More... | |
void | RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState) |
Enables or disables the specified RCC interrupts. More... | |
void | RCC_USBCLKConfig (uint32_t RCC_USBCLKSource) |
Configures the USB clock (USBCLK). More... | |
void | RCC_ADCCLKConfig (uint32_t RCC_PCLK2) |
Configures the ADC clock (ADCCLK). More... | |
void | RCC_LSEConfig (uint8_t RCC_LSE) |
Configures the External Low Speed oscillator (LSE). More... | |
void | RCC_LSICmd (FunctionalState NewState) |
Enables or disables the Internal Low Speed oscillator (LSI). More... | |
void | RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource) |
Configures the RTC clock (RTCCLK). More... | |
void | RCC_RTCCLKCmd (FunctionalState NewState) |
Enables or disables the RTC clock. More... | |
void | RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks) |
Returns the frequencies of different on chip clocks. More... | |
void | RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState) |
Enables or disables the AHB peripheral clock. More... | |
void | RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
Enables or disables the High Speed APB (APB2) peripheral clock. More... | |
void | RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
Enables or disables the Low Speed APB (APB1) peripheral clock. More... | |
void | RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState) |
Forces or releases High Speed APB (APB2) peripheral reset. More... | |
void | RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState) |
Forces or releases Low Speed APB (APB1) peripheral reset. More... | |
void | RCC_BackupResetCmd (FunctionalState NewState) |
Forces or releases the Backup domain reset. More... | |
void | RCC_ClockSecuritySystemCmd (FunctionalState NewState) |
Enables or disables the Clock Security System. More... | |
void | RCC_MCOConfig (uint8_t RCC_MCO) |
Selects the clock source to output on MCO pin. More... | |
FlagStatus | RCC_GetFlagStatus (uint8_t RCC_FLAG) |
Checks whether the specified RCC flag is set or not. More... | |
void | RCC_ClearFlag (void) |
Clears the RCC reset flags. More... | |
ITStatus | RCC_GetITStatus (uint8_t RCC_IT) |
Checks whether the specified RCC interrupt has occurred or not. More... | |
void | RCC_ClearITPendingBit (uint8_t RCC_IT) |
Clears the RCC's interrupt pending bits. More... | |
This file contains all the functions prototypes for the RCC firmware library.
THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
Definition in file stm32f10x_rcc.h.