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lpc17xx_mcpwm.c
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1 /***********************************************************************/
21 /* Peripheral group ----------------------------------------------------------- */
26 /* Includes ------------------------------------------------------------------- */
27 #include "lpc17xx_mcpwm.h"
28 #include "lpc17xx_clkpwr.h"
29 
30 /* If this source file built with example, the LPC17xx FW library configuration
31  * file in each example directory ("lpc17xx_libcfg.h") must be included,
32  * otherwise the default FW library configuration file must be included instead
33  */
34 #ifdef __BUILD_WITH_EXAMPLE__
35 #include "lpc17xx_libcfg.h"
36 #else
37 #include "lpc17xx_libcfg_default.h"
38 #endif /* __BUILD_WITH_EXAMPLE__ */
39 
40 
41 #ifdef _MCPWM
42 
43 /* Public Functions ----------------------------------------------------------- */
48 /*********************************************************************/
54 void MCPWM_Init(LPC_MCPWM_TypeDef *MCPWMx)
55 {
56 
57  /* Turn On MCPWM PCLK */
58  CLKPWR_ConfigPPWR (CLKPWR_PCONP_PCMC, ENABLE);
59  /* As default, peripheral clock for MCPWM module
60  * is set to FCCLK / 2 */
61  // CLKPWR_SetPCLKDiv(CLKPWR_PCLKSEL_MC, CLKPWR_PCLKSEL_CCLK_DIV_2);
62 
63  MCPWMx->MCCAP_CLR = MCPWM_CAPCLR_CAP(0) | MCPWM_CAPCLR_CAP(1) | MCPWM_CAPCLR_CAP(2);
64  MCPWMx->MCINTFLAG_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \
65  | MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \
66  | MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2);
67  MCPWMx->MCINTEN_CLR = MCPWM_INT_ILIM(0) | MCPWM_INT_ILIM(1) | MCPWM_INT_ILIM(2) \
68  | MCPWM_INT_IMAT(0) | MCPWM_INT_IMAT(1) | MCPWM_INT_IMAT(2) \
69  | MCPWM_INT_ICAP(0) | MCPWM_INT_ICAP(1) | MCPWM_INT_ICAP(2);
70 }
71 
72 
73 /*********************************************************************/
84 void MCPWM_ConfigChannel(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
85  MCPWM_CHANNEL_CFG_Type * channelSetup)
86 {
87  if ((channelNum >= 0) && (channelNum <= 2)) {
88  if (channelNum == 0) {
89  MCPWMx->MCTIM0 = channelSetup->channelTimercounterValue;
90  MCPWMx->MCPER0 = channelSetup->channelPeriodValue;
91  MCPWMx->MCPW0 = channelSetup->channelPulsewidthValue;
92  } else if (channelNum == 1) {
93  MCPWMx->MCTIM1 = channelSetup->channelTimercounterValue;
94  MCPWMx->MCPER1 = channelSetup->channelPeriodValue;
95  MCPWMx->MCPW1 = channelSetup->channelPulsewidthValue;
96  } else if (channelNum == 2) {
97  MCPWMx->MCTIM2 = channelSetup->channelTimercounterValue;
98  MCPWMx->MCPER2 = channelSetup->channelPeriodValue;
99  MCPWMx->MCPW2 = channelSetup->channelPulsewidthValue;
100  } else {
101  return;
102  }
103 
104  if (channelSetup->channelType /* == MCPWM_CHANNEL_CENTER_MODE */){
105  MCPWMx->MCCON_SET = MCPWM_CON_CENTER(channelNum);
106  } else {
107  MCPWMx->MCCON_CLR = MCPWM_CON_CENTER(channelNum);
108  }
109 
110  if (channelSetup->channelPolarity /* == MCPWM_CHANNEL_PASSIVE_HI */){
111  MCPWMx->MCCON_SET = MCPWM_CON_POLAR(channelNum);
112  } else {
113  MCPWMx->MCCON_CLR = MCPWM_CON_POLAR(channelNum);
114  }
115 
116  if (channelSetup->channelDeadtimeEnable /* == ENABLE */){
117  MCPWMx->MCCON_SET = MCPWM_CON_DTE(channelNum);
118  MCPWMx->MCDEADTIME &= ~(MCPWM_DT(channelNum, 0x3FF));
119  MCPWMx->MCDEADTIME |= MCPWM_DT(channelNum, channelSetup->channelDeadtimeValue);
120  } else {
121  MCPWMx->MCCON_CLR = MCPWM_CON_DTE(channelNum);
122  }
123 
124  if (channelSetup->channelUpdateEnable /* == ENABLE */){
125  MCPWMx->MCCON_CLR = MCPWM_CON_DISUP(channelNum);
126  } else {
127  MCPWMx->MCCON_SET = MCPWM_CON_DISUP(channelNum);
128  }
129  }
130 }
131 
132 
133 /*********************************************************************/
144 void MCPWM_WriteToShadow(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
145  MCPWM_CHANNEL_CFG_Type *channelSetup)
146 {
147  if (channelNum == 0){
148  MCPWMx->MCPER0 = channelSetup->channelPeriodValue;
149  MCPWMx->MCPW0 = channelSetup->channelPulsewidthValue;
150  } else if (channelNum == 1) {
151  MCPWMx->MCPER1 = channelSetup->channelPeriodValue;
152  MCPWMx->MCPW1 = channelSetup->channelPulsewidthValue;
153  } else if (channelNum == 2) {
154  MCPWMx->MCPER2 = channelSetup->channelPeriodValue;
155  MCPWMx->MCPW2 = channelSetup->channelPulsewidthValue;
156  }
157 }
158 
159 
160 
161 /*********************************************************************/
172 void MCPWM_ConfigCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
173  MCPWM_CAPTURE_CFG_Type *captureConfig)
174 {
175  if ((channelNum >= 0) && (channelNum <= 2)) {
176 
177  if (captureConfig->captureFalling /* == ENABLE */) {
178  MCPWMx->MCCAPCON_SET = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum);
179  } else {
180  MCPWMx->MCCAPCON_CLR = MCPWM_CAPCON_CAPMCI_FE(captureConfig->captureChannel, channelNum);
181  }
182 
183  if (captureConfig->captureRising /* == ENABLE */) {
184  MCPWMx->MCCAPCON_SET = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum);
185  } else {
186  MCPWMx->MCCAPCON_CLR = MCPWM_CAPCON_CAPMCI_RE(captureConfig->captureChannel, channelNum);
187  }
188 
189  if (captureConfig->timerReset /* == ENABLE */){
190  MCPWMx->MCCAPCON_SET = MCPWM_CAPCON_RT(captureConfig->captureChannel);
191  } else {
192  MCPWMx->MCCAPCON_CLR = MCPWM_CAPCON_RT(captureConfig->captureChannel);
193  }
194 
195  if (captureConfig->hnfEnable /* == ENABLE */){
196  MCPWMx->MCCAPCON_SET = MCPWM_CAPCON_HNFCAP(channelNum);
197  } else {
198  MCPWMx->MCCAPCON_CLR = MCPWM_CAPCON_HNFCAP(channelNum);
199  }
200  }
201 }
202 
203 
204 /*********************************************************************/
211 void MCPWM_ClearCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel)
212 {
213  MCPWMx->MCCAP_CLR = MCPWM_CAPCLR_CAP(captureChannel);
214 }
215 
216 /*********************************************************************/
223 uint32_t MCPWM_GetCapture(LPC_MCPWM_TypeDef *MCPWMx, uint32_t captureChannel)
224 {
225  if (captureChannel == 0){
226  return (MCPWMx->MCCR0);
227  } else if (captureChannel == 1) {
228  return (MCPWMx->MCCR1);
229  } else if (captureChannel == 2) {
230  return (MCPWMx->MCCR2);
231  }
232  return (0);
233 }
234 
235 
236 /*********************************************************************/
249 void MCPWM_CountConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channelNum,
250  uint32_t countMode, MCPWM_COUNT_CFG_Type *countConfig)
251 {
252  if ((channelNum >= 0) && (channelNum <= 2)) {
253  if (countMode /* == ENABLE */){
254  MCPWMx->MCCNTCON_SET = MCPWM_CNTCON_CNTR(channelNum);
255  if (countConfig->countFalling /* == ENABLE */) {
256  MCPWMx->MCCNTCON_SET = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum);
257  } else {
258  MCPWMx->MCCNTCON_CLR = MCPWM_CNTCON_TCMCI_FE(countConfig->counterChannel,channelNum);
259  }
260  if (countConfig->countRising /* == ENABLE */) {
261  MCPWMx->MCCNTCON_SET = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum);
262  } else {
263  MCPWMx->MCCNTCON_CLR = MCPWM_CNTCON_TCMCI_RE(countConfig->counterChannel,channelNum);
264  }
265  } else {
266  MCPWMx->MCCNTCON_CLR = MCPWM_CNTCON_CNTR(channelNum);
267  }
268  }
269 }
270 
271 
272 /*********************************************************************/
287 void MCPWM_Start(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channel0,
288  uint32_t channel1, uint32_t channel2)
289 {
290  uint32_t regVal = 0;
291  regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \
292  | (channel2 ? MCPWM_CON_RUN(2) : 0);
293  MCPWMx->MCCON_SET = regVal;
294 }
295 
296 
297 /*********************************************************************/
312 void MCPWM_Stop(LPC_MCPWM_TypeDef *MCPWMx, uint32_t channel0,
313  uint32_t channel1, uint32_t channel2)
314 {
315  uint32_t regVal = 0;
316  regVal = (channel0 ? MCPWM_CON_RUN(0) : 0) | (channel1 ? MCPWM_CON_RUN(1) : 0) \
317  | (channel2 ? MCPWM_CON_RUN(2) : 0);
318  MCPWMx->MCCON_CLR = regVal;
319 }
320 
321 
322 /*********************************************************************/
331 void MCPWM_ACMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t acMode)
332 {
333  if (acMode){
334  MCPWMx->MCCON_SET = MCPWM_CON_ACMODE;
335  } else {
336  MCPWMx->MCCON_CLR = MCPWM_CON_ACMODE;
337  }
338 }
339 
340 
341 /*********************************************************************/
366 void MCPWM_DCMode(LPC_MCPWM_TypeDef *MCPWMx, uint32_t dcMode,
367  uint32_t outputInvered, uint32_t outputPattern)
368 {
369  if (dcMode){
370  MCPWMx->MCCON_SET = MCPWM_CON_DCMODE;
371  } else {
372  MCPWMx->MCCON_CLR = MCPWM_CON_DCMODE;
373  }
374 
375  if (outputInvered) {
376  MCPWMx->MCCON_SET = MCPWM_CON_INVBDC;
377  } else {
378  MCPWMx->MCCON_CLR = MCPWM_CON_INVBDC;
379  }
380 
381  MCPWMx->MCCCP = outputPattern;
382 }
383 
384 
385 /*********************************************************************/
407 void MCPWM_IntConfig(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType, FunctionalState NewState)
408 {
409  if (NewState) {
410  MCPWMx->MCINTEN_SET = ulIntType;
411  } else {
412  MCPWMx->MCINTEN_CLR = ulIntType;
413  }
414 }
415 
416 
417 /*********************************************************************/
435 void MCPWM_IntSet(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType)
436 {
437  MCPWMx->MCINTFLAG_SET = ulIntType;
438 }
439 
440 
441 /*********************************************************************/
459 void MCPWM_IntClear(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType)
460 {
461  MCPWMx->MCINTFLAG_CLR = ulIntType;
462 }
463 
464 
465 /*********************************************************************/
482 FlagStatus MCPWM_GetIntStatus(LPC_MCPWM_TypeDef *MCPWMx, uint32_t ulIntType)
483 {
484  return ((MCPWMx->MCINTFLAG & ulIntType) ? SET : RESET);
485 }
486 
491 #endif /* _MCPWM */
492 
497 /* --------------------------------- End Of File ------------------------------ */