CMSIS Cortex-M3 Core Peripheral Access Layer Header File. More...

#include <stdint.h>

Classes
struct	NVIC_Type
	Nested Vectored Interrupt Controller (NVIC) register structure definition. More...

struct	SCB_Type
	System Control Block (SCB) register structure definition. More...

struct	SysTick_Type
	System Tick Timer (SysTick) register structure definition. More...

struct	ITM_Type
	Instrumentation Trace Macrocell (ITM) register structure definition. More...

struct	InterruptType_Type
	Instrumentation Trace Macrocell (ITM) register structure definition. More...

struct	CoreDebug_Type
	Core Debug register structure definition. More...

Macros
#define	__CM3_CMSIS_VERSION_MAIN (0x01)

#define	__CM3_CMSIS_VERSION_SUB (0x30)

#define	__CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| __CM3_CMSIS_VERSION_SUB)

#define	__CORTEX_M (0x03)

#define	__NVIC_PRIO_BITS 4

#define	__I volatile const

#define	__O volatile

#define	__IO volatile

#define	SCB_CPUID_IMPLEMENTER_Pos 24

#define	SCB_CPUID_IMPLEMENTER_Msk (0xFFul << SCB_CPUID_IMPLEMENTER_Pos)

#define	SCB_CPUID_VARIANT_Pos 20

#define	SCB_CPUID_VARIANT_Msk (0xFul << SCB_CPUID_VARIANT_Pos)

#define	SCB_CPUID_PARTNO_Pos 4

#define	SCB_CPUID_PARTNO_Msk (0xFFFul << SCB_CPUID_PARTNO_Pos)

#define	SCB_CPUID_REVISION_Pos 0

#define	SCB_CPUID_REVISION_Msk (0xFul << SCB_CPUID_REVISION_Pos)

#define	SCB_ICSR_NMIPENDSET_Pos 31

#define	SCB_ICSR_NMIPENDSET_Msk (1ul << SCB_ICSR_NMIPENDSET_Pos)

#define	SCB_ICSR_PENDSVSET_Pos 28

#define	SCB_ICSR_PENDSVSET_Msk (1ul << SCB_ICSR_PENDSVSET_Pos)

#define	SCB_ICSR_PENDSVCLR_Pos 27

#define	SCB_ICSR_PENDSVCLR_Msk (1ul << SCB_ICSR_PENDSVCLR_Pos)

#define	SCB_ICSR_PENDSTSET_Pos 26

#define	SCB_ICSR_PENDSTSET_Msk (1ul << SCB_ICSR_PENDSTSET_Pos)

#define	SCB_ICSR_PENDSTCLR_Pos 25

#define	SCB_ICSR_PENDSTCLR_Msk (1ul << SCB_ICSR_PENDSTCLR_Pos)

#define	SCB_ICSR_ISRPREEMPT_Pos 23

#define	SCB_ICSR_ISRPREEMPT_Msk (1ul << SCB_ICSR_ISRPREEMPT_Pos)

#define	SCB_ICSR_ISRPENDING_Pos 22

#define	SCB_ICSR_ISRPENDING_Msk (1ul << SCB_ICSR_ISRPENDING_Pos)

#define	SCB_ICSR_VECTPENDING_Pos 12

#define	SCB_ICSR_VECTPENDING_Msk (0x1FFul << SCB_ICSR_VECTPENDING_Pos)

#define	SCB_ICSR_RETTOBASE_Pos 11

#define	SCB_ICSR_RETTOBASE_Msk (1ul << SCB_ICSR_RETTOBASE_Pos)

#define	SCB_ICSR_VECTACTIVE_Pos 0

#define	SCB_ICSR_VECTACTIVE_Msk (0x1FFul << SCB_ICSR_VECTACTIVE_Pos)

#define	SCB_VTOR_TBLBASE_Pos 29

#define	SCB_VTOR_TBLBASE_Msk (0x1FFul << SCB_VTOR_TBLBASE_Pos)

#define	SCB_VTOR_TBLOFF_Pos 7

#define	SCB_VTOR_TBLOFF_Msk (0x3FFFFFul << SCB_VTOR_TBLOFF_Pos)

#define	SCB_AIRCR_VECTKEY_Pos 16

#define	SCB_AIRCR_VECTKEY_Msk (0xFFFFul << SCB_AIRCR_VECTKEY_Pos)

#define	SCB_AIRCR_VECTKEYSTAT_Pos 16

#define	SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFul << SCB_AIRCR_VECTKEYSTAT_Pos)

#define	SCB_AIRCR_ENDIANESS_Pos 15

#define	SCB_AIRCR_ENDIANESS_Msk (1ul << SCB_AIRCR_ENDIANESS_Pos)

#define	SCB_AIRCR_PRIGROUP_Pos 8

#define	SCB_AIRCR_PRIGROUP_Msk (7ul << SCB_AIRCR_PRIGROUP_Pos)

#define	SCB_AIRCR_SYSRESETREQ_Pos 2

#define	SCB_AIRCR_SYSRESETREQ_Msk (1ul << SCB_AIRCR_SYSRESETREQ_Pos)

#define	SCB_AIRCR_VECTCLRACTIVE_Pos 1

#define	SCB_AIRCR_VECTCLRACTIVE_Msk (1ul << SCB_AIRCR_VECTCLRACTIVE_Pos)

#define	SCB_AIRCR_VECTRESET_Pos 0

#define	SCB_AIRCR_VECTRESET_Msk (1ul << SCB_AIRCR_VECTRESET_Pos)

#define	SCB_SCR_SEVONPEND_Pos 4

#define	SCB_SCR_SEVONPEND_Msk (1ul << SCB_SCR_SEVONPEND_Pos)

#define	SCB_SCR_SLEEPDEEP_Pos 2

#define	SCB_SCR_SLEEPDEEP_Msk (1ul << SCB_SCR_SLEEPDEEP_Pos)

#define	SCB_SCR_SLEEPONEXIT_Pos 1

#define	SCB_SCR_SLEEPONEXIT_Msk (1ul << SCB_SCR_SLEEPONEXIT_Pos)

#define	SCB_CCR_STKALIGN_Pos 9

#define	SCB_CCR_STKALIGN_Msk (1ul << SCB_CCR_STKALIGN_Pos)

#define	SCB_CCR_BFHFNMIGN_Pos 8

#define	SCB_CCR_BFHFNMIGN_Msk (1ul << SCB_CCR_BFHFNMIGN_Pos)

#define	SCB_CCR_DIV_0_TRP_Pos 4

#define	SCB_CCR_DIV_0_TRP_Msk (1ul << SCB_CCR_DIV_0_TRP_Pos)

#define	SCB_CCR_UNALIGN_TRP_Pos 3

#define	SCB_CCR_UNALIGN_TRP_Msk (1ul << SCB_CCR_UNALIGN_TRP_Pos)

#define	SCB_CCR_USERSETMPEND_Pos 1

#define	SCB_CCR_USERSETMPEND_Msk (1ul << SCB_CCR_USERSETMPEND_Pos)

#define	SCB_CCR_NONBASETHRDENA_Pos 0

#define	SCB_CCR_NONBASETHRDENA_Msk (1ul << SCB_CCR_NONBASETHRDENA_Pos)

#define	SCB_SHCSR_USGFAULTENA_Pos 18

#define	SCB_SHCSR_USGFAULTENA_Msk (1ul << SCB_SHCSR_USGFAULTENA_Pos)

#define	SCB_SHCSR_BUSFAULTENA_Pos 17

#define	SCB_SHCSR_BUSFAULTENA_Msk (1ul << SCB_SHCSR_BUSFAULTENA_Pos)

#define	SCB_SHCSR_MEMFAULTENA_Pos 16

#define	SCB_SHCSR_MEMFAULTENA_Msk (1ul << SCB_SHCSR_MEMFAULTENA_Pos)

#define	SCB_SHCSR_SVCALLPENDED_Pos 15

#define	SCB_SHCSR_SVCALLPENDED_Msk (1ul << SCB_SHCSR_SVCALLPENDED_Pos)

#define	SCB_SHCSR_BUSFAULTPENDED_Pos 14

#define	SCB_SHCSR_BUSFAULTPENDED_Msk (1ul << SCB_SHCSR_BUSFAULTPENDED_Pos)

#define	SCB_SHCSR_MEMFAULTPENDED_Pos 13

#define	SCB_SHCSR_MEMFAULTPENDED_Msk (1ul << SCB_SHCSR_MEMFAULTPENDED_Pos)

#define	SCB_SHCSR_USGFAULTPENDED_Pos 12

#define	SCB_SHCSR_USGFAULTPENDED_Msk (1ul << SCB_SHCSR_USGFAULTPENDED_Pos)

#define	SCB_SHCSR_SYSTICKACT_Pos 11

#define	SCB_SHCSR_SYSTICKACT_Msk (1ul << SCB_SHCSR_SYSTICKACT_Pos)

#define	SCB_SHCSR_PENDSVACT_Pos 10

#define	SCB_SHCSR_PENDSVACT_Msk (1ul << SCB_SHCSR_PENDSVACT_Pos)

#define	SCB_SHCSR_MONITORACT_Pos 8

#define	SCB_SHCSR_MONITORACT_Msk (1ul << SCB_SHCSR_MONITORACT_Pos)

#define	SCB_SHCSR_SVCALLACT_Pos 7

#define	SCB_SHCSR_SVCALLACT_Msk (1ul << SCB_SHCSR_SVCALLACT_Pos)

#define	SCB_SHCSR_USGFAULTACT_Pos 3

#define	SCB_SHCSR_USGFAULTACT_Msk (1ul << SCB_SHCSR_USGFAULTACT_Pos)

#define	SCB_SHCSR_BUSFAULTACT_Pos 1

#define	SCB_SHCSR_BUSFAULTACT_Msk (1ul << SCB_SHCSR_BUSFAULTACT_Pos)

#define	SCB_SHCSR_MEMFAULTACT_Pos 0

#define	SCB_SHCSR_MEMFAULTACT_Msk (1ul << SCB_SHCSR_MEMFAULTACT_Pos)

#define	SCB_CFSR_USGFAULTSR_Pos 16

#define	SCB_CFSR_USGFAULTSR_Msk (0xFFFFul << SCB_CFSR_USGFAULTSR_Pos)

#define	SCB_CFSR_BUSFAULTSR_Pos 8

#define	SCB_CFSR_BUSFAULTSR_Msk (0xFFul << SCB_CFSR_BUSFAULTSR_Pos)

#define	SCB_CFSR_MEMFAULTSR_Pos 0

#define	SCB_CFSR_MEMFAULTSR_Msk (0xFFul << SCB_CFSR_MEMFAULTSR_Pos)

#define	SCB_HFSR_DEBUGEVT_Pos 31

#define	SCB_HFSR_DEBUGEVT_Msk (1ul << SCB_HFSR_DEBUGEVT_Pos)

#define	SCB_HFSR_FORCED_Pos 30

#define	SCB_HFSR_FORCED_Msk (1ul << SCB_HFSR_FORCED_Pos)

#define	SCB_HFSR_VECTTBL_Pos 1

#define	SCB_HFSR_VECTTBL_Msk (1ul << SCB_HFSR_VECTTBL_Pos)

#define	SCB_DFSR_EXTERNAL_Pos 4

#define	SCB_DFSR_EXTERNAL_Msk (1ul << SCB_DFSR_EXTERNAL_Pos)

#define	SCB_DFSR_VCATCH_Pos 3

#define	SCB_DFSR_VCATCH_Msk (1ul << SCB_DFSR_VCATCH_Pos)

#define	SCB_DFSR_DWTTRAP_Pos 2

#define	SCB_DFSR_DWTTRAP_Msk (1ul << SCB_DFSR_DWTTRAP_Pos)

#define	SCB_DFSR_BKPT_Pos 1

#define	SCB_DFSR_BKPT_Msk (1ul << SCB_DFSR_BKPT_Pos)

#define	SCB_DFSR_HALTED_Pos 0

#define	SCB_DFSR_HALTED_Msk (1ul << SCB_DFSR_HALTED_Pos)

#define	SysTick_CTRL_COUNTFLAG_Pos 16

#define	SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos)

#define	SysTick_CTRL_CLKSOURCE_Pos 2

#define	SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos)

#define	SysTick_CTRL_TICKINT_Pos 1

#define	SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos)

#define	SysTick_CTRL_ENABLE_Pos 0

#define	SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos)

#define	SysTick_LOAD_RELOAD_Pos 0

#define	SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos)

#define	SysTick_VAL_CURRENT_Pos 0

#define	SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)

#define	SysTick_CALIB_NOREF_Pos 31

#define	SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos)

#define	SysTick_CALIB_SKEW_Pos 30

#define	SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos)

#define	SysTick_CALIB_TENMS_Pos 0

#define	SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos)

#define	ITM_TPR_PRIVMASK_Pos 0

#define	ITM_TPR_PRIVMASK_Msk (0xFul << ITM_TPR_PRIVMASK_Pos)

#define	ITM_TCR_BUSY_Pos 23

#define	ITM_TCR_BUSY_Msk (1ul << ITM_TCR_BUSY_Pos)

#define	ITM_TCR_ATBID_Pos 16

#define	ITM_TCR_ATBID_Msk (0x7Ful << ITM_TCR_ATBID_Pos)

#define	ITM_TCR_TSPrescale_Pos 8

#define	ITM_TCR_TSPrescale_Msk (3ul << ITM_TCR_TSPrescale_Pos)

#define	ITM_TCR_SWOENA_Pos 4

#define	ITM_TCR_SWOENA_Msk (1ul << ITM_TCR_SWOENA_Pos)

#define	ITM_TCR_DWTENA_Pos 3

#define	ITM_TCR_DWTENA_Msk (1ul << ITM_TCR_DWTENA_Pos)

#define	ITM_TCR_SYNCENA_Pos 2

#define	ITM_TCR_SYNCENA_Msk (1ul << ITM_TCR_SYNCENA_Pos)

#define	ITM_TCR_TSENA_Pos 1

#define	ITM_TCR_TSENA_Msk (1ul << ITM_TCR_TSENA_Pos)

#define	ITM_TCR_ITMENA_Pos 0

#define	ITM_TCR_ITMENA_Msk (1ul << ITM_TCR_ITMENA_Pos)

#define	ITM_IWR_ATVALIDM_Pos 0

#define	ITM_IWR_ATVALIDM_Msk (1ul << ITM_IWR_ATVALIDM_Pos)

#define	ITM_IRR_ATREADYM_Pos 0

#define	ITM_IRR_ATREADYM_Msk (1ul << ITM_IRR_ATREADYM_Pos)

#define	ITM_IMCR_INTEGRATION_Pos 0

#define	ITM_IMCR_INTEGRATION_Msk (1ul << ITM_IMCR_INTEGRATION_Pos)

#define	ITM_LSR_ByteAcc_Pos 2

#define	ITM_LSR_ByteAcc_Msk (1ul << ITM_LSR_ByteAcc_Pos)

#define	ITM_LSR_Access_Pos 1

#define	ITM_LSR_Access_Msk (1ul << ITM_LSR_Access_Pos)

#define	ITM_LSR_Present_Pos 0

#define	ITM_LSR_Present_Msk (1ul << ITM_LSR_Present_Pos)

#define	InterruptType_ICTR_INTLINESNUM_Pos 0

#define	InterruptType_ICTR_INTLINESNUM_Msk (0x1Ful << InterruptType_ICTR_INTLINESNUM_Pos)

#define	InterruptType_ACTLR_DISFOLD_Pos 2

#define	InterruptType_ACTLR_DISFOLD_Msk (1ul << InterruptType_ACTLR_DISFOLD_Pos)

#define	InterruptType_ACTLR_DISDEFWBUF_Pos 1

#define	InterruptType_ACTLR_DISDEFWBUF_Msk (1ul << InterruptType_ACTLR_DISDEFWBUF_Pos)

#define	InterruptType_ACTLR_DISMCYCINT_Pos 0

#define	InterruptType_ACTLR_DISMCYCINT_Msk (1ul << InterruptType_ACTLR_DISMCYCINT_Pos)

#define	CoreDebug_DHCSR_DBGKEY_Pos 16

#define	CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFul << CoreDebug_DHCSR_DBGKEY_Pos)

#define	CoreDebug_DHCSR_S_RESET_ST_Pos 25

#define	CoreDebug_DHCSR_S_RESET_ST_Msk (1ul << CoreDebug_DHCSR_S_RESET_ST_Pos)

#define	CoreDebug_DHCSR_S_RETIRE_ST_Pos 24

#define	CoreDebug_DHCSR_S_RETIRE_ST_Msk (1ul << CoreDebug_DHCSR_S_RETIRE_ST_Pos)

#define	CoreDebug_DHCSR_S_LOCKUP_Pos 19

#define	CoreDebug_DHCSR_S_LOCKUP_Msk (1ul << CoreDebug_DHCSR_S_LOCKUP_Pos)

#define	CoreDebug_DHCSR_S_SLEEP_Pos 18

#define	CoreDebug_DHCSR_S_SLEEP_Msk (1ul << CoreDebug_DHCSR_S_SLEEP_Pos)

#define	CoreDebug_DHCSR_S_HALT_Pos 17

#define	CoreDebug_DHCSR_S_HALT_Msk (1ul << CoreDebug_DHCSR_S_HALT_Pos)

#define	CoreDebug_DHCSR_S_REGRDY_Pos 16

#define	CoreDebug_DHCSR_S_REGRDY_Msk (1ul << CoreDebug_DHCSR_S_REGRDY_Pos)

#define	CoreDebug_DHCSR_C_SNAPSTALL_Pos 5

#define	CoreDebug_DHCSR_C_SNAPSTALL_Msk (1ul << CoreDebug_DHCSR_C_SNAPSTALL_Pos)

#define	CoreDebug_DHCSR_C_MASKINTS_Pos 3

#define	CoreDebug_DHCSR_C_MASKINTS_Msk (1ul << CoreDebug_DHCSR_C_MASKINTS_Pos)

#define	CoreDebug_DHCSR_C_STEP_Pos 2

#define	CoreDebug_DHCSR_C_STEP_Msk (1ul << CoreDebug_DHCSR_C_STEP_Pos)

#define	CoreDebug_DHCSR_C_HALT_Pos 1

#define	CoreDebug_DHCSR_C_HALT_Msk (1ul << CoreDebug_DHCSR_C_HALT_Pos)

#define	CoreDebug_DHCSR_C_DEBUGEN_Pos 0

#define	CoreDebug_DHCSR_C_DEBUGEN_Msk (1ul << CoreDebug_DHCSR_C_DEBUGEN_Pos)

#define	CoreDebug_DCRSR_REGWnR_Pos 16

#define	CoreDebug_DCRSR_REGWnR_Msk (1ul << CoreDebug_DCRSR_REGWnR_Pos)

#define	CoreDebug_DCRSR_REGSEL_Pos 0

#define	CoreDebug_DCRSR_REGSEL_Msk (0x1Ful << CoreDebug_DCRSR_REGSEL_Pos)

#define	CoreDebug_DEMCR_TRCENA_Pos 24

#define	CoreDebug_DEMCR_TRCENA_Msk (1ul << CoreDebug_DEMCR_TRCENA_Pos)

#define	CoreDebug_DEMCR_MON_REQ_Pos 19

#define	CoreDebug_DEMCR_MON_REQ_Msk (1ul << CoreDebug_DEMCR_MON_REQ_Pos)

#define	CoreDebug_DEMCR_MON_STEP_Pos 18

#define	CoreDebug_DEMCR_MON_STEP_Msk (1ul << CoreDebug_DEMCR_MON_STEP_Pos)

#define	CoreDebug_DEMCR_MON_PEND_Pos 17

#define	CoreDebug_DEMCR_MON_PEND_Msk (1ul << CoreDebug_DEMCR_MON_PEND_Pos)

#define	CoreDebug_DEMCR_MON_EN_Pos 16

#define	CoreDebug_DEMCR_MON_EN_Msk (1ul << CoreDebug_DEMCR_MON_EN_Pos)

#define	CoreDebug_DEMCR_VC_HARDERR_Pos 10

#define	CoreDebug_DEMCR_VC_HARDERR_Msk (1ul << CoreDebug_DEMCR_VC_HARDERR_Pos)

#define	CoreDebug_DEMCR_VC_INTERR_Pos 9

#define	CoreDebug_DEMCR_VC_INTERR_Msk (1ul << CoreDebug_DEMCR_VC_INTERR_Pos)

#define	CoreDebug_DEMCR_VC_BUSERR_Pos 8

#define	CoreDebug_DEMCR_VC_BUSERR_Msk (1ul << CoreDebug_DEMCR_VC_BUSERR_Pos)

#define	CoreDebug_DEMCR_VC_STATERR_Pos 7

#define	CoreDebug_DEMCR_VC_STATERR_Msk (1ul << CoreDebug_DEMCR_VC_STATERR_Pos)

#define	CoreDebug_DEMCR_VC_CHKERR_Pos 6

#define	CoreDebug_DEMCR_VC_CHKERR_Msk (1ul << CoreDebug_DEMCR_VC_CHKERR_Pos)

#define	CoreDebug_DEMCR_VC_NOCPERR_Pos 5

#define	CoreDebug_DEMCR_VC_NOCPERR_Msk (1ul << CoreDebug_DEMCR_VC_NOCPERR_Pos)

#define	CoreDebug_DEMCR_VC_MMERR_Pos 4

#define	CoreDebug_DEMCR_VC_MMERR_Msk (1ul << CoreDebug_DEMCR_VC_MMERR_Pos)

#define	CoreDebug_DEMCR_VC_CORERESET_Pos 0

#define	CoreDebug_DEMCR_VC_CORERESET_Msk (1ul << CoreDebug_DEMCR_VC_CORERESET_Pos)

#define	SCS_BASE (0xE000E000)

#define	ITM_BASE (0xE0000000)

#define	CoreDebug_BASE (0xE000EDF0)

#define	SysTick_BASE (SCS_BASE + 0x0010)

#define	NVIC_BASE (SCS_BASE + 0x0100)

#define	SCB_BASE (SCS_BASE + 0x0D00)

#define	InterruptType ((InterruptType_Type *) SCS_BASE)

#define	SCB ((SCB_Type *) SCB_BASE)

#define	SysTick ((SysTick_Type *) SysTick_BASE)

#define	NVIC ((NVIC_Type *) NVIC_BASE)

#define	ITM ((ITM_Type *) ITM_BASE)

#define	CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)

#define	ITM_RXBUFFER_EMPTY 0x5AA55AA5

Variables
volatile int	ITM_RxBuffer

Detailed Description

CMSIS Cortex-M3 Core Peripheral Access Layer Header File.

Version: V1.30

Date: 30. October 2009

: ARM Limited (ARM) is supplying this software for use with Cortex-M processor based microcontrollers. This file can be freely distributed within development tools that are supporting such ARM based processors.

: THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

Definition in file core_cm3.h.

Classes

Macros

Variables

Detailed Description