47 #define ACR_LATENCY_Mask ((uint32_t)0x00000038)
48 #define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
49 #define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
52 #define ACR_PRFTBS_Mask ((uint32_t)0x00000020)
55 #define CR_PG_Set ((uint32_t)0x00000001)
56 #define CR_PG_Reset ((uint32_t)0x00001FFE)
57 #define CR_PER_Set ((uint32_t)0x00000002)
58 #define CR_PER_Reset ((uint32_t)0x00001FFD)
59 #define CR_MER_Set ((uint32_t)0x00000004)
60 #define CR_MER_Reset ((uint32_t)0x00001FFB)
61 #define CR_OPTPG_Set ((uint32_t)0x00000010)
62 #define CR_OPTPG_Reset ((uint32_t)0x00001FEF)
63 #define CR_OPTER_Set ((uint32_t)0x00000020)
64 #define CR_OPTER_Reset ((uint32_t)0x00001FDF)
65 #define CR_STRT_Set ((uint32_t)0x00000040)
66 #define CR_LOCK_Set ((uint32_t)0x00000080)
69 #define RDPRT_Mask ((uint32_t)0x00000002)
70 #define WRP0_Mask ((uint32_t)0x000000FF)
71 #define WRP1_Mask ((uint32_t)0x0000FF00)
72 #define WRP2_Mask ((uint32_t)0x00FF0000)
73 #define WRP3_Mask ((uint32_t)0xFF000000)
74 #define OB_USER_BFB2 ((uint16_t)0x0008)
77 #define RDP_Key ((uint16_t)0x00A5)
78 #define FLASH_KEY1 ((uint32_t)0x45670123)
79 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
82 #define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
85 #define EraseTimeout ((uint32_t)0x000B0000)
86 #define ProgramTimeout ((uint32_t)0x00002000)
266 tmpreg |= FLASH_Latency;
288 FLASH->ACR |= FLASH_HalfCycleAccess;
307 FLASH->ACR |= FLASH_PrefetchBuffer;
354 void FLASH_UnlockBank2(
void)
405 void FLASH_LockBank2(
void)
434 FLASH->AR = Page_Address;
452 FLASH->AR2 = Page_Address;
470 FLASH->AR = Page_Address;
650 OB->RDP = (uint16_t)rdptmp;
684 __IO uint32_t tmp = 0;
700 *(
__IO uint16_t*)Address = (uint16_t)Data;
710 *(
__IO uint16_t*) tmp = Data >> 16;
736 *(
__IO uint16_t*)Address = (uint16_t)Data;
760 *(
__IO uint16_t*) tmp = Data >> 16;
785 *(
__IO uint16_t*)Address = (uint16_t)Data;
795 *(
__IO uint16_t*) tmp = Data >> 16;
820 *(
__IO uint16_t*)Address = (uint16_t)Data;
830 *(
__IO uint16_t*) tmp = Data >> 16;
875 *(
__IO uint16_t*)Address = Data;
890 *(
__IO uint16_t*)Address = Data;
907 *(
__IO uint16_t*)Address = Data;
943 *(
__IO uint16_t*)Address = Data;
977 uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
984 FLASH_Pages = (uint32_t)(~FLASH_Pages);
985 WRP0_Data = (uint16_t)(FLASH_Pages &
WRP0_Mask);
986 WRP1_Data = (uint16_t)((FLASH_Pages &
WRP1_Mask) >> 8);
987 WRP2_Data = (uint16_t)((FLASH_Pages &
WRP2_Mask) >> 16);
988 WRP3_Data = (uint16_t)((FLASH_Pages &
WRP3_Mask) >> 24);
999 if(WRP0_Data != 0xFF)
1001 OB->WRP0 = WRP0_Data;
1008 OB->WRP1 = WRP1_Data;
1015 OB->WRP2 = WRP2_Data;
1023 OB->WRP3 = WRP3_Data;
1139 OB->USER = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)0xF8)));
1188 if(FLASH_BOOT == FLASH_BOOT_Bank1)
1219 return (uint32_t)(
FLASH->OBR >> 2);
1231 return (uint32_t)(
FLASH->WRPR);
1245 readoutstatus =
SET;
1249 readoutstatus =
RESET;
1251 return readoutstatus;
1297 if((FLASH_IT & 0x80000000) != 0x0)
1302 FLASH->CR2 |= (FLASH_IT & 0x7FFFFFFF);
1307 FLASH->CR2 &= ~(uint32_t)(FLASH_IT & 0x7FFFFFFF);
1315 FLASH->CR |= FLASH_IT;
1320 FLASH->CR &= ~(uint32_t)FLASH_IT;
1331 FLASH->CR |= FLASH_IT;
1336 FLASH->CR &= ~(uint32_t)FLASH_IT;
1377 if((FLASH_FLAG & 0x80000000) != 0x0)
1379 if((
FLASH->SR2 & FLASH_FLAG) != (uint32_t)
RESET)
1390 if((
FLASH->SR & FLASH_FLAG) != (uint32_t)
RESET)
1416 if((
FLASH->SR & FLASH_FLAG) != (uint32_t)
RESET)
1449 if((FLASH_FLAG & 0x80000000) != 0x0)
1452 FLASH->SR2 = FLASH_FLAG;
1457 FLASH->SR = FLASH_FLAG;
1465 FLASH->SR = FLASH_FLAG;
1557 if((
FLASH->SR2 & (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF))
1563 if((
FLASH->SR2 & (FLASH_FLAG_BANK2_PGERR & 0x7FFFFFFF)) != 0)
1569 if((
FLASH->SR2 & (FLASH_FLAG_BANK2_WRPRTERR & 0x7FFFFFFF)) != 0 )
1602 while((status ==
FLASH_BUSY) && (Timeout != 0x00))
1607 if(Timeout == 0x00 )
1635 if(Timeout == 0x00 )
1651 FLASH_Status FLASH_WaitForLastBank2Operation(uint32_t Timeout)
1656 status = FLASH_GetBank2Status();
1658 while((status == (FLASH_FLAG_BANK2_BSY & 0x7FFFFFFF)) && (Timeout != 0x00))
1660 status = FLASH_GetBank2Status();
1663 if(Timeout == 0x00 )