24 #ifndef __STM32F10x_ADC_H
25 #define __STM32F10x_ADC_H
83 #define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
84 ((PERIPH) == ADC2) || \
87 #define IS_ADC_DMA_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
94 #define ADC_Mode_Independent ((uint32_t)0x00000000)
95 #define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
96 #define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
97 #define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
98 #define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
99 #define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
100 #define ADC_Mode_RegSimult ((uint32_t)0x00060000)
101 #define ADC_Mode_FastInterl ((uint32_t)0x00070000)
102 #define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
103 #define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
105 #define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
106 ((MODE) == ADC_Mode_RegInjecSimult) || \
107 ((MODE) == ADC_Mode_RegSimult_AlterTrig) || \
108 ((MODE) == ADC_Mode_InjecSimult_FastInterl) || \
109 ((MODE) == ADC_Mode_InjecSimult_SlowInterl) || \
110 ((MODE) == ADC_Mode_InjecSimult) || \
111 ((MODE) == ADC_Mode_RegSimult) || \
112 ((MODE) == ADC_Mode_FastInterl) || \
113 ((MODE) == ADC_Mode_SlowInterl) || \
114 ((MODE) == ADC_Mode_AlterTrig))
123 #define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
124 #define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)
125 #define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000)
126 #define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000)
127 #define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000)
128 #define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000)
130 #define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)
131 #define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
133 #define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000)
134 #define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000)
135 #define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000)
136 #define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000)
137 #define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000)
138 #define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000)
140 #define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
141 ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
142 ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
143 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
144 ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
145 ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
146 ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO) || \
147 ((REGTRIG) == ADC_ExternalTrigConv_None) || \
148 ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
149 ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
150 ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
151 ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
152 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
153 ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3))
162 #define ADC_DataAlign_Right ((uint32_t)0x00000000)
163 #define ADC_DataAlign_Left ((uint32_t)0x00000800)
164 #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
165 ((ALIGN) == ADC_DataAlign_Left))
174 #define ADC_Channel_0 ((uint8_t)0x00)
175 #define ADC_Channel_1 ((uint8_t)0x01)
176 #define ADC_Channel_2 ((uint8_t)0x02)
177 #define ADC_Channel_3 ((uint8_t)0x03)
178 #define ADC_Channel_4 ((uint8_t)0x04)
179 #define ADC_Channel_5 ((uint8_t)0x05)
180 #define ADC_Channel_6 ((uint8_t)0x06)
181 #define ADC_Channel_7 ((uint8_t)0x07)
182 #define ADC_Channel_8 ((uint8_t)0x08)
183 #define ADC_Channel_9 ((uint8_t)0x09)
184 #define ADC_Channel_10 ((uint8_t)0x0A)
185 #define ADC_Channel_11 ((uint8_t)0x0B)
186 #define ADC_Channel_12 ((uint8_t)0x0C)
187 #define ADC_Channel_13 ((uint8_t)0x0D)
188 #define ADC_Channel_14 ((uint8_t)0x0E)
189 #define ADC_Channel_15 ((uint8_t)0x0F)
190 #define ADC_Channel_16 ((uint8_t)0x10)
191 #define ADC_Channel_17 ((uint8_t)0x11)
193 #define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
194 #define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
196 #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
197 ((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
198 ((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
199 ((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
200 ((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
201 ((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
202 ((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
203 ((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
204 ((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17))
213 #define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
214 #define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
215 #define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
216 #define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
217 #define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
218 #define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
219 #define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
220 #define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
221 #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1Cycles5) || \
222 ((TIME) == ADC_SampleTime_7Cycles5) || \
223 ((TIME) == ADC_SampleTime_13Cycles5) || \
224 ((TIME) == ADC_SampleTime_28Cycles5) || \
225 ((TIME) == ADC_SampleTime_41Cycles5) || \
226 ((TIME) == ADC_SampleTime_55Cycles5) || \
227 ((TIME) == ADC_SampleTime_71Cycles5) || \
228 ((TIME) == ADC_SampleTime_239Cycles5))
237 #define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)
238 #define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)
239 #define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)
240 #define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000)
241 #define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000)
243 #define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
244 #define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
245 #define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
247 #define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000)
248 #define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000)
249 #define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000)
250 #define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000)
251 #define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000)
253 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
254 ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
255 ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
256 ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
257 ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
258 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
259 ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4) || \
260 ((INJTRIG) == ADC_ExternalTrigInjecConv_None) || \
261 ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
262 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
263 ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
264 ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
265 ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4))
274 #define ADC_InjectedChannel_1 ((uint8_t)0x14)
275 #define ADC_InjectedChannel_2 ((uint8_t)0x18)
276 #define ADC_InjectedChannel_3 ((uint8_t)0x1C)
277 #define ADC_InjectedChannel_4 ((uint8_t)0x20)
278 #define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
279 ((CHANNEL) == ADC_InjectedChannel_2) || \
280 ((CHANNEL) == ADC_InjectedChannel_3) || \
281 ((CHANNEL) == ADC_InjectedChannel_4))
290 #define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
291 #define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
292 #define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
293 #define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
294 #define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
295 #define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
296 #define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
298 #define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
299 ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
300 ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
301 ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
302 ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
303 ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
304 ((WATCHDOG) == ADC_AnalogWatchdog_None))
313 #define ADC_IT_EOC ((uint16_t)0x0220)
314 #define ADC_IT_AWD ((uint16_t)0x0140)
315 #define ADC_IT_JEOC ((uint16_t)0x0480)
317 #define IS_ADC_IT(IT) ((((IT) & (uint16_t)0xF81F) == 0x00) && ((IT) != 0x00))
319 #define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
320 ((IT) == ADC_IT_JEOC))
329 #define ADC_FLAG_AWD ((uint8_t)0x01)
330 #define ADC_FLAG_EOC ((uint8_t)0x02)
331 #define ADC_FLAG_JEOC ((uint8_t)0x04)
332 #define ADC_FLAG_JSTRT ((uint8_t)0x08)
333 #define ADC_FLAG_STRT ((uint8_t)0x10)
334 #define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xE0) == 0x00) && ((FLAG) != 0x00))
335 #define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
336 ((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
337 ((FLAG) == ADC_FLAG_STRT))
346 #define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
356 #define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
366 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
376 #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
387 #define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
396 #define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
406 #define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))