Nested Vectored Interrupt Controller (NVIC) register structure definition. More...

#include <core_cm3.h>

Detailed Description

Nested Vectored Interrupt Controller (NVIC) register structure definition.

Definition at line 137 of file core_cm3.h.

Member Data Documentation

__IO uint32_t NVIC_Type::IABR[8]

Offset: 0x200 Interrupt Active bit Register

Definition at line 147 of file core_cm3.h.

__IO uint32_t NVIC_Type::ICER[8]

Offset: 0x080 Interrupt Clear Enable Register

Definition at line 141 of file core_cm3.h.

__IO uint32_t NVIC_Type::ICPR[8]

Offset: 0x180 Interrupt Clear Pending Register

Definition at line 145 of file core_cm3.h.

__IO uint8_t NVIC_Type::IP[240]

Offset: 0x300 Interrupt Priority Register (8Bit wide)

Definition at line 149 of file core_cm3.h.

__IO uint32_t NVIC_Type::ISER[8]

Offset: 0x000 Interrupt Set Enable Register

Definition at line 139 of file core_cm3.h.

__IO uint32_t NVIC_Type::ISPR[8]

Offset: 0x100 Interrupt Set Pending Register

Definition at line 143 of file core_cm3.h.

uint32_t NVIC_Type::RESERVED0[24]

Definition at line 140 of file core_cm3.h.

uint32_t NVIC_Type::RESERVED2[24]

Definition at line 144 of file core_cm3.h.

uint32_t NVIC_Type::RESERVED3[24]

Definition at line 146 of file core_cm3.h.

uint32_t NVIC_Type::RESERVED4[56]

Definition at line 148 of file core_cm3.h.

uint32_t NVIC_Type::RESERVED5[644]

Definition at line 150 of file core_cm3.h.

uint32_t NVIC_Type::RSERVED1[24]

Definition at line 142 of file core_cm3.h.

__O uint32_t NVIC_Type::STIR

Offset: 0xE00 Software Trigger Interrupt Register

Definition at line 151 of file core_cm3.h.

The documentation for this struct was generated from the following file: