Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
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software_version_and_target_device
betaFALSE build_version2258646
date_generatedTue Oct 30 19:43:42 2018 os_platformWIN64
product_versionVivado v2018.2 (64-bit) project_idf9b5b1fa02064cb2a49dc5b591326345
project_iteration41 random_id31afbe3c-c042-44b6-bd0e-c9c8e4067204
registration_id211600466_0_0_408 route_designTRUE
target_devicexc7a35t target_familyartix7
target_packageftg256 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-5930K CPU @ 3.50GHz cpu_speed3499 MHz
os_nameMicrosoft Windows 8 or later , 64-bit os_releasemajor release (build 9200)
system_ram34.000 GB total_processors1

vivado_usage
gui_handlers
abstractfileview_close=1 addilaprobespopup_ok=8 alertsetupdebugdialog_dont_show_this_dialog_again=1 basedialog_cancel=38
basedialog_close=1 basedialog_ok=152 basedialog_yes=21 closeplanner_yes=1
cmdmsgdialog_ok=22 cmdmsgdialog_open_messages_view=1 constraintschooserpanel_create_file=1 constraintschooserpanel_file_table=4
coretreetablepanel_core_tree_table=22 createconstraintsfilepanel_file_name=2 createsrcfiledialog_file_name=7 customizecoredialog_ip_location=1
debugwizard_1_net=1 debugwizard_advanced_trigger=4 debugwizard_assign_all_clock_domains=1 debugwizard_capture_control=4
debugwizard_chipscope_tree_table=14 debugwizard_continue_debugging=1 debugwizard_disconnect_all_nets_and_remove_debug=10 debugwizard_find_nets_to_add=21
debugwizard_find_results=1 debugwizard_more_info=2 debugwizard_netlist_view=2 debugwizard_only_debug_new_nets=5
debugwizard_open_in_specified_layout=1 debugwizard_sample_of_data_depth=16 debugwizard_select_clock_domain=1 expruntreepanel_exp_run_tree_table=5
filesetpanel_file_set_panel_tree=184 findandpicknetsdialog_nets_tree_table_panel=28 flownavigatortreepanel_flow_navigator_tree=284 fpgachooser_fpga_table=2
gettingstartedview_create_new_project=1 gettingstartedview_open_project=3 graphicalview_zoom_fit=1 graphicalview_zoom_in=45
graphicalview_zoom_out=38 hacgccoefilewidget_browse=1 hacgctabbedpane_tabbed_pane=1 hardwaredashboardoptionspanel_layer_tree=2
hardwaredashboardview_cell_name_for_debug_core=2 hardwaredeviceproppanels_specify_probes_file=1 hardwareilawaveformview_run_trigger_for_this_ila_core=6 hardwareilawaveformview_run_trigger_immediate_for_this_ila_core=1
hardwareilawaveformview_stop_trigger_for_this_ila_core=1 hardwaretreepanel_hardware_tree_table=27 hcodeeditor_search_text_combo_box=19 hfolderchooserhelpers_up_one_level=8
hpopuptitle_close=1 ilaprobetablepanel_add_probe=5 ilaprobetablepanel_set_trigger_condition_to_global=1 instancemenu_floorplanning=2
languagetemplatesdialog_templates_tree=27 launchpanel_dont_show_this_dialog_again=1 mainmenumgr_edit=4 mainmenumgr_file=2
mainmenumgr_flow=5 mainmenumgr_project=1 mainmenumgr_settings=3 mainmenumgr_tools=6
mainmenumgr_window=8 messagewithoptiondialog_dont_show_this_dialog_again=6 msgtreepanel_message_view_tree=11 msgview_error_messages=2
navigabletimingreporttab_timing_report_navigation_tree=3 netlisttreeview_netlist_tree=12 pacommandnames_add_sources=7 pacommandnames_auto_connect_target=8
pacommandnames_auto_fit_selection=2 pacommandnames_auto_update_hier=23 pacommandnames_close_project=1 pacommandnames_design_runs_window=4
pacommandnames_edit_constraint_sets=1 pacommandnames_goto_implemented_design=2 pacommandnames_goto_instantiation=1 pacommandnames_goto_netlist_design=1
pacommandnames_language_templates=1 pacommandnames_open_hardware_manager=1 pacommandnames_project_summary=4 pacommandnames_report_ip_status=1
pacommandnames_reports_window=3 pacommandnames_run_bitgen=1 pacommandnames_run_synthesis=1 pacommandnames_run_trigger=4
pacommandnames_select_area=2 pacommandnames_simulation_run=1 pacommandnames_stop_trigger=1 pacommandnames_zoom_fit=1
pacommandnames_zoom_in=42 pacommandnames_zoom_out=20 paviews_code=2 paviews_dashboard=16
paviews_device=20 paviews_ip_catalog=1 paviews_project_summary=2 probesview_probes_tree=10
probevaluetablepanel_text_field=2 programdebugtab_open_target=3 programdebugtab_program_device=1 programfpgadialog_program=44
programfpgadialog_specify_bitstream_file=1 programfpgadialog_specify_debug_probes_file=6 progressdialog_background=3 projectnamechooser_choose_project_location=1
projectnamechooser_project_name=1 projectsummarydrcpanel_open_drc_report=1 projecttab_close_design=5 projecttab_reload=11
rdicommands_delete=1 rdicommands_properties=6 rdiviews_waveform_viewer=4 rungadget_show_error=1
rungadget_show_error_and_critical_warning_messages=1 rungadget_show_warning_and_error_messages_in_messages=1 saveprojectutils_save=12 schematicview_next=6
schematicview_previous=5 schematicview_regenerate=5 schematicview_remove=1 selectmenu_highlight=2
selectmenu_mark=2 simpleoutputproductdialog_generate_output_products_immediately=11 srcchooserpanel_create_file=6 srcmenu_ip_documentation=2
srcmenu_ip_hierarchy=22 stalerundialog_open_design=1 stalerundialog_run_synthesis=1 statemonitor_reset_run=2
statemonitor_reset_step=1 syntheticagettingstartedview_recent_projects=4 syntheticastatemonitor_cancel=3 taskbanner_close=10
timingsumresultstab_show_only_failing_checks=1 touchpointsurveydialog_yes=1 triggersetuppanel_table=10 triggerstatuspanel_run_trigger_for_this_ila_core=3
triggerstatuspanel_stop_trigger_for_this_ila_core=3 waveformnametree_waveform_name_tree=9 waveformview_add=4
java_command_handlers
addsources=8 autoconnecttarget=8 closeproject=1 coreview=3
customizecore=6 debugwizardcmdhandler=37 editconstraintsets=1 editdelete=6
editpaste=6 editproperties=6 fliptoviewtasksynthesis=1 launchprogramfpga=50
newhardwaredashboard=8 newproject=1 openexistingreport=1 openhardwaremanager=60
openproject=3 openrecenttarget=7 programdevice=51 projectsummary=4
recustomizecore=13 reportipstatus=1 reporttimingsummary=5 runbitgen=58
runimplementation=9 runsynthesis=28 runtrigger=13 runtriggerimmediate=1
savedesign=13 savefileproxyhandler=3 showsource=1 showview=31
stoptrigger=5 tclfind=1 timingconstraintswizard=2 toggleautofitselection=2
toggleselectareamode=2 toolssettings=4 toolstemplates=1 viewlayoutcmd=2
viewtaskimplementation=4 viewtaskprogramanddebug=3 viewtaskprojectmanager=44 viewtaskrtlanalysis=1
viewtasksynthesis=5 zoomfit=1 zoomin=49 zoomout=22
other_data
guimode=9
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=11 export_simulation_ies=11
export_simulation_modelsim=11 export_simulation_questa=11 export_simulation_riviera=11 export_simulation_vcs=11
export_simulation_xsim=11 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Verilog srcsetcount=5 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=5 totalsynthesisruns=5

unisim_transformation
post_unisim_transformation
bufg=3 carry4=25 fdre=262 fdse=6
gnd=36 ibuf=1 lut1=10 lut2=59
lut3=23 lut4=57 lut5=22 lut6=42
mmcme2_adv=1 obuf=28 oddr=1 ramb18e1=2
ramb36e1=1 srl16e=2 vcc=25
pre_unisim_transformation
bufg=3 carry4=25 fdre=262 fdse=6
gnd=36 ibuf=1 lut1=10 lut2=59
lut3=23 lut4=57 lut5=22 lut6=42
mmcme2_adv=1 obuf=28 oddr=1 ramb18e1=2
ramb36e1=1 srl16e=2 vcc=25

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=1 bram_ports_newly_gated=1 bram_ports_total=6 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=262 srls_augmented=0
srls_newly_gated=0 srls_total=2

ip_statistics
blk_mem_gen_v8_4_1/1
c_addra_width=11 c_addrb_width=11 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_count_18k_bram=1 c_count_36k_bram=0 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=0
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=0 c_est_power_summary=Estimated Power for IP _ 2.4801 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=0 c_has_enb=0
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=0
c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=text_fb.mem
c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=0 c_mem_type=1 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=2048 c_read_depth_b=2048 c_read_width_a=9 c_read_width_b=9
c_rst_priority_a=CE c_rst_priority_b=CE c_rstram_a=0 c_rstram_b=0
c_sim_collision_check=ALL c_use_bram_block=0 c_use_byte_wea=0 c_use_byte_web=0
c_use_default_data=1 c_use_ecc=0 c_use_softecc=0 c_use_uram=0
c_wea_width=1 c_web_width=1 c_write_depth_a=2048 c_write_depth_b=2048
c_write_mode_a=NO_CHANGE c_write_mode_b=WRITE_FIRST c_write_width_a=9 c_write_width_b=9
c_xdevicefamily=artix7 core_container=false iptotal=1 x_ipcorerevision=1
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=blk_mem_gen x_ipproduct=Vivado 2018.2
x_ipsimlanguage=VERILOG x_ipvendor=xilinx.com x_ipversion=8.4
blk_mem_gen_v8_4_1/2
c_addra_width=14 c_addrb_width=14 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_count_18k_bram=1 c_count_36k_bram=0 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=0
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=0 c_est_power_summary=Estimated Power for IP _ 2.25395 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=0 c_has_enb=0
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=0
c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=vram_font.mem
c_init_file_name=[user-defined] c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=1 c_mem_type=1 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=16384 c_read_depth_b=16384 c_read_width_a=1 c_read_width_b=1
c_rst_priority_a=CE c_rst_priority_b=CE c_rstram_a=0 c_rstram_b=0
c_sim_collision_check=ALL c_use_bram_block=0 c_use_byte_wea=0 c_use_byte_web=0
c_use_default_data=1 c_use_ecc=0 c_use_softecc=0 c_use_uram=0
c_wea_width=1 c_web_width=1 c_write_depth_a=16384 c_write_depth_b=16384
c_write_mode_a=NO_CHANGE c_write_mode_b=WRITE_FIRST c_write_width_a=1 c_write_width_b=1
c_xdevicefamily=artix7 core_container=false iptotal=1 x_ipcorerevision=1
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=blk_mem_gen x_ipproduct=Vivado 2018.2
x_ipsimlanguage=VERILOG x_ipvendor=xilinx.com x_ipversion=8.4
clk_wiz_v6_0_1_0_0/1
clkin1_period=20.000 clkin2_period=10.0 clock_mgr_type=NA component_name=clocks
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=2 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=false
fifo_generator_v13_2_2/1
c_add_ngc_constraint=0 c_application_type_axis=0 c_application_type_rach=0 c_application_type_rdch=0
c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0 c_axi_addr_width=32
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1 c_axi_data_width=64
c_axi_id_width=1 c_axi_len_width=8 c_axi_lock_width=1 c_axi_ruser_width=1
c_axi_type=1 c_axi_wuser_width=1 c_axis_tdata_width=8 c_axis_tdest_width=1
c_axis_tid_width=1 c_axis_tkeep_width=1 c_axis_tstrb_width=1 c_axis_tuser_width=4
c_axis_type=0 c_common_clock=0 c_count_type=0 c_data_count_width=10
c_default_value=BlankString c_din_width=24 c_din_width_axis=1 c_din_width_rach=32
c_din_width_rdch=64 c_din_width_wach=1 c_din_width_wdch=64 c_din_width_wrch=2
c_dout_rst_val=0 c_dout_width=24 c_en_safety_ckt=1 c_enable_rlocs=0
c_enable_rst_sync=1 c_error_injection_type=0 c_error_injection_type_axis=0 c_error_injection_type_rach=0
c_error_injection_type_rdch=0 c_error_injection_type_wach=0 c_error_injection_type_wdch=0 c_error_injection_type_wrch=0
c_family=artix7 c_full_flags_rst_val=1 c_has_almost_empty=0 c_has_almost_full=0
c_has_axi_aruser=0 c_has_axi_awuser=0 c_has_axi_buser=0 c_has_axi_id=0
c_has_axi_rd_channel=1 c_has_axi_ruser=0 c_has_axi_wr_channel=1 c_has_axi_wuser=0
c_has_axis_tdata=1 c_has_axis_tdest=0 c_has_axis_tid=0 c_has_axis_tkeep=0
c_has_axis_tlast=0 c_has_axis_tready=1 c_has_axis_tstrb=0 c_has_axis_tuser=1
c_has_backup=0 c_has_data_count=0 c_has_data_counts_axis=0 c_has_data_counts_rach=0
c_has_data_counts_rdch=0 c_has_data_counts_wach=0 c_has_data_counts_wdch=0 c_has_data_counts_wrch=0
c_has_int_clk=0 c_has_master_ce=0 c_has_meminit_file=0 c_has_overflow=0
c_has_prog_flags_axis=0 c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_wach=0
c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_slave_ce=0 c_has_srst=0 c_has_underflow=0
c_has_valid=0 c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0
c_implementation_type=2 c_implementation_type_axis=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_wach=1 c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_init_wr_pntr_val=0
c_interface_type=0 c_memory_type=1 c_mif_file_name=BlankString c_msgon_val=1
c_optimization_mode=0 c_overflow_low=0 c_power_saving_mode=0 c_preload_latency=2
c_preload_regs=1 c_prim_fifo_type=1kx36 c_prim_fifo_type_axis=1kx18 c_prim_fifo_type_rach=512x36
c_prim_fifo_type_rdch=1kx36 c_prim_fifo_type_wach=512x36 c_prim_fifo_type_wdch=1kx36 c_prim_fifo_type_wrch=512x36
c_prog_empty_thresh_assert_val=2 c_prog_empty_thresh_assert_val_axis=1022 c_prog_empty_thresh_assert_val_rach=1022 c_prog_empty_thresh_assert_val_rdch=1022
c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022 c_prog_empty_thresh_negate_val=3
c_prog_empty_type=0 c_prog_empty_type_axis=0 c_prog_empty_type_rach=0 c_prog_empty_type_rdch=0
c_prog_empty_type_wach=0 c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0 c_prog_full_thresh_assert_val=480
c_prog_full_thresh_assert_val_axis=1023 c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023 c_prog_full_thresh_assert_val_wach=1023
c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023 c_prog_full_thresh_negate_val=479 c_prog_full_type=1
c_prog_full_type_axis=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0 c_prog_full_type_wach=0
c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_rach_type=0 c_rd_data_count_width=10
c_rd_depth=1024 c_rd_freq=1 c_rd_pntr_width=10 c_rdch_type=0
c_reg_slice_mode_axis=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0 c_reg_slice_mode_wach=0
c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_select_xpm=0 c_synchronizer_stage=2
c_underflow_low=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_use_dout_rst=1 c_use_ecc=0 c_use_ecc_axis=0 c_use_ecc_rach=0
c_use_ecc_rdch=0 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_embedded_reg=1 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_use_pipeline_reg=0
c_valid_low=0 c_wach_type=0 c_wdch_type=0 c_wr_ack_low=0
c_wr_data_count_width=10 c_wr_depth=1024 c_wr_depth_axis=1024 c_wr_depth_rach=16
c_wr_depth_rdch=1024 c_wr_depth_wach=16 c_wr_depth_wdch=1024 c_wr_depth_wrch=16
c_wr_freq=1 c_wr_pntr_width=10 c_wr_pntr_width_axis=10 c_wr_pntr_width_rach=4
c_wr_pntr_width_rdch=10 c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4
c_wr_response_latency=1 c_wrch_type=0 core_container=false iptotal=1
x_ipcorerevision=2 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=fifo_generator
x_ipproduct=Vivado 2018.2 x_ipsimlanguage=VERILOG x_ipvendor=xilinx.com x_ipversion=13.2
xpm_cdc_gray/1
core_container=NA dest_sync_ff=2 init_sync_ff=0 iptotal=2
reg_output=1 sim_assert_chk=0 sim_lossless_gray_chk=0 version=0
width=10
xpm_cdc_single/1
core_container=NA dest_sync_ff=5 init_sync_ff=0 iptotal=2
sim_assert_chk=0 src_input_reg=0 version=0
xpm_cdc_sync_rst/1
core_container=NA def_val=1'b1 dest_sync_ff=5 init=1
init_sync_ff=0 iptotal=2 sim_assert_chk=0 version=0

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 pdrc-153=1 plholdvio-2=1 rtstat-10=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
pdrc-190=1 timing-14=1 timing-38=2 timing-6=4

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.003746 clocks=0.002961
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=High confidence_level_overall=Medium customer=TBD customer_class=TBD
devstatic=0.072034 die=xc7a35tftg256-1 dsp_output_toggle=12.500000 dynamic=0.107212
effective_thetaja=4.9 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=0.001251 input_toggle=12.500000
junction_temp=25.9 (C) logic=0.000316 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mmcm=0.100107 netlist_net_matched=NA
off-chip_power=0.000000 on-chip_power=0.179245 output_enable=1.000000 output_load=5.000000
output_toggle=12.500000 package=ftg256 pct_clock_constrained=2.000000 pct_inputs_defined=100
platform=nt64 process=typical ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.000312
simulation_file=None speedgrade=-1 static_prob=False temp_grade=commercial
thetajb=8.2 (C/W) thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=4.9 user_junc_temp=25.9 (C) user_thetajb=8.2 (C/W) user_thetasa=4.6 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.055474 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.012628 vccaux_total_current=0.068103 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000302 vccbram_static_current=0.000211 vccbram_total_current=0.000514 vccbram_voltage=1.000000
vccint_dynamic_current=0.005927 vccint_static_current=0.009791 vccint_total_current=0.015718 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.000342 vcco33_static_current=0.001000 vcco33_total_current=0.001342 vcco33_voltage=3.300000
version=2018.2

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=3 bufgctrl_util_percentage=9.38
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=20.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=90 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=50 block_ram_tile_fixed=0 block_ram_tile_used=2 block_ram_tile_util_percentage=4.00
ramb18_available=100 ramb18_fixed=0 ramb18_used=2 ramb18_util_percentage=2.00
ramb18e1_only_used=2 ramb36_fifo_available=50 ramb36_fifo_fixed=0 ramb36_fifo_used=1
ramb36_fifo_util_percentage=2.00 ramb36e1_only_used=1
primitives
bufg_functional_category=Clock bufg_used=3 carry4_functional_category=CarryLogic carry4_used=22
fdre_functional_category=Flop & Latch fdre_used=257 fdse_functional_category=Flop & Latch fdse_used=5
ibuf_functional_category=IO ibuf_used=1 lut1_functional_category=LUT lut1_used=9
lut2_functional_category=LUT lut2_used=49 lut3_functional_category=LUT lut3_used=22
lut4_functional_category=LUT lut4_used=56 lut5_functional_category=LUT lut5_used=22
lut6_functional_category=LUT lut6_used=41 mmcme2_adv_functional_category=Clock mmcme2_adv_used=1
obuf_functional_category=IO obuf_used=28 oddr_functional_category=IO oddr_used=1
ramb18e1_functional_category=Block Memory ramb18e1_used=2 ramb36e1_functional_category=Block Memory ramb36e1_used=1
srl16e_functional_category=Distributed Memory srl16e_used=2
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=20800 lut_as_logic_fixed=0
lut_as_logic_used=160 lut_as_logic_util_percentage=0.77 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=2 lut_as_memory_util_percentage=0.02 lut_as_shift_register_fixed=0 lut_as_shift_register_used=2
register_as_flip_flop_available=41600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=262 register_as_flip_flop_util_percentage=0.63
register_as_latch_available=41600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=20800 slice_luts_fixed=0 slice_luts_used=162 slice_luts_util_percentage=0.78
slice_registers_available=41600 slice_registers_fixed=0 slice_registers_used=262 slice_registers_util_percentage=0.63
fully_used_lut_ff_pairs_fixed=0.63 fully_used_lut_ff_pairs_used=21 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=20800 lut_as_logic_fixed=0 lut_as_logic_used=160 lut_as_logic_util_percentage=0.77
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=2 lut_as_memory_util_percentage=0.02
lut_as_shift_register_fixed=0 lut_as_shift_register_used=2 lut_ff_pairs_with_one_unused_flip_flop_fixed=2 lut_ff_pairs_with_one_unused_flip_flop_used=56
lut_ff_pairs_with_one_unused_lut_output_fixed=56 lut_ff_pairs_with_one_unused_lut_output_used=67 lut_flip_flop_pairs_available=20800 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=92 lut_flip_flop_pairs_util_percentage=0.44 slice_available=8150 slice_fixed=0
slice_used=80 slice_util_percentage=0.98 slicel_fixed=0 slicel_used=58
slicem_fixed=0 slicem_used=22 unique_control_sets_used=13 using_o5_and_o6_fixed=13
using_o5_and_o6_used=0 using_o5_output_only_fixed=0 using_o5_output_only_used=2 using_o6_output_only_fixed=2
using_o6_output_only_used=0
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=696439 bogomips=0 bram18=2 bram36=1
bufg=0 bufr=0 congestion_level=0 ctrls=13
dsp=0 effort=2 estimated_expansions=253062 ff=262
global_clocks=3 high_fanout_nets=0 iob=29 lut=180
movable_instances=576 nets=657 pins=3323 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a35tftg256-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=uGPU -verilog_define=default::[not_specified]
usage
elapsed=00:00:31s hls_ip=0 memory_gain=507.438MB memory_peak=842.480MB