Nugget
arch_arm_store.h
1 // Copyright (c) Electronic Arts Inc. All rights reserved.
4 
5 
6 #ifndef EASTL_ATOMIC_INTERNAL_ARCH_ARM_STORE_H
7 #define EASTL_ATOMIC_INTERNAL_ARCH_ARM_STORE_H
8 
9 #if defined(EA_PRAGMA_ONCE_SUPPORTED)
10  #pragma once
11 #endif
12 
13 
15 //
16 // void EASTL_ARCH_ATOMIC_STORE_*_N(type, type * ptr, type val)
17 //
18 #if defined(EA_COMPILER_MSVC)
19 
20 
21  #define EASTL_ARCH_ATOMIC_ARM_STORE_N(integralType, bits, type, ptr, val) \
22  EA_PREPROCESSOR_JOIN(__iso_volatile_store, bits)(EASTL_ATOMIC_VOLATILE_INTEGRAL_CAST(integralType, (ptr)), EASTL_ATOMIC_TYPE_PUN_CAST(integralType, (val)))
23 
24 
25  #define EASTL_ARCH_ATOMIC_ARM_STORE_8(type, ptr, val) \
26  EASTL_ARCH_ATOMIC_ARM_STORE_N(__int8, 8, type, ptr, val)
27 
28  #define EASTL_ARCH_ATOMIC_ARM_STORE_16(type, ptr, val) \
29  EASTL_ARCH_ATOMIC_ARM_STORE_N(__int16, 16, type, ptr, val)
30 
31  #define EASTL_ARCH_ATOMIC_ARM_STORE_32(type, ptr, val) \
32  EASTL_ARCH_ATOMIC_ARM_STORE_N(__int32, 32, type, ptr, val)
33 
34 
35  #if defined(EA_PROCESSOR_ARM64)
36 
37  #define EASTL_ARCH_ATOMIC_ARM_STORE_64(type, ptr, val) \
38  EASTL_ARCH_ATOMIC_ARM_STORE_N(__int64, 64, type, ptr, val)
39 
40  #endif
41 
42 
43  #define EASTL_ARCH_ATOMIC_ARM_STORE_128(type, ptr, val, MemoryOrder) \
44  { \
45  type exchange128; EA_UNUSED(exchange128); \
46  EA_PREPROCESSOR_JOIN(EA_PREPROCESSOR_JOIN(EASTL_ATOMIC_EXCHANGE_, MemoryOrder), _128)(type, exchange128, ptr, val); \
47  }
48 
49 
50  #define EASTL_ARCH_ATOMIC_STORE_RELAXED_8(type, ptr, val) \
51  EASTL_ARCH_ATOMIC_ARM_STORE_8(type, ptr, val)
52 
53  #define EASTL_ARCH_ATOMIC_STORE_RELAXED_16(type, ptr, val) \
54  EASTL_ARCH_ATOMIC_ARM_STORE_16(type, ptr, val)
55 
56  #define EASTL_ARCH_ATOMIC_STORE_RELAXED_32(type, ptr, val) \
57  EASTL_ARCH_ATOMIC_ARM_STORE_32(type, ptr, val)
58 
59  #define EASTL_ARCH_ATOMIC_STORE_RELAXED_128(type, ptr, val) \
60  EASTL_ARCH_ATOMIC_ARM_STORE_128(type, ptr, val, RELAXED)
61 
62 
63  #define EASTL_ARCH_ATOMIC_STORE_RELEASE_8(type, ptr, val) \
64  EASTL_ATOMIC_CPU_MB(); \
65  EASTL_ARCH_ATOMIC_ARM_STORE_8(type, ptr, val)
66 
67  #define EASTL_ARCH_ATOMIC_STORE_RELEASE_16(type, ptr, val) \
68  EASTL_ATOMIC_CPU_MB(); \
69  EASTL_ARCH_ATOMIC_ARM_STORE_16(type, ptr, val)
70 
71  #define EASTL_ARCH_ATOMIC_STORE_RELEASE_32(type, ptr, val) \
72  EASTL_ATOMIC_CPU_MB(); \
73  EASTL_ARCH_ATOMIC_ARM_STORE_32(type, ptr, val)
74 
75  #define EASTL_ARCH_ATOMIC_STORE_RELEASE_128(type, ptr, val) \
76  EASTL_ARCH_ATOMIC_ARM_STORE_128(type, ptr, val, RELEASE)
77 
78 
79  #define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_8(type, ptr, val) \
80  EASTL_ATOMIC_CPU_MB(); \
81  EASTL_ARCH_ATOMIC_ARM_STORE_8(type, ptr, val) ; \
82  EASTL_ATOMIC_CPU_MB()
83 
84  #define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_16(type, ptr, val) \
85  EASTL_ATOMIC_CPU_MB(); \
86  EASTL_ARCH_ATOMIC_ARM_STORE_16(type, ptr, val); \
87  EASTL_ATOMIC_CPU_MB()
88 
89  #define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_32(type, ptr, val) \
90  EASTL_ATOMIC_CPU_MB(); \
91  EASTL_ARCH_ATOMIC_ARM_STORE_32(type, ptr, val); \
92  EASTL_ATOMIC_CPU_MB()
93 
94  #define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_128(type, ptr, val) \
95  EASTL_ARCH_ATOMIC_ARM_STORE_128(type, ptr, val, SEQ_CST)
96 
97 
98  #if defined(EA_PROCESSOR_ARM32)
99 
100 
101  #define EASTL_ARCH_ATOMIC_STORE_RELAXED_64(type, ptr, val) \
102  { \
103  type retExchange64; EA_UNUSED(retExchange64); \
104  EASTL_ATOMIC_EXCHANGE_RELAXED_64(type, retExchange64, ptr, val); \
105  }
106 
107  #define EASTL_ARCH_ATOMIC_STORE_RELEASE_64(type, ptr, val) \
108  { \
109  type retExchange64; EA_UNUSED(retExchange64); \
110  EASTL_ATOMIC_EXCHANGE_RELEASE_64(type, retExchange64, ptr, val); \
111  }
112 
113  #define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_64(type, ptr, val) \
114  { \
115  type retExchange64; EA_UNUSED(retExchange64); \
116  EASTL_ATOMIC_EXCHANGE_SEQ_CST_64(type, retExchange64, ptr, val); \
117  }
118 
119 
120  #elif defined(EA_PROCESSOR_ARM64)
121 
122 
123  #define EASTL_ARCH_ATOMIC_STORE_RELAXED_64(type, ptr, val) \
124  EASTL_ARCH_ATOMIC_ARM_STORE_64(type, ptr, val)
125 
126  #define EASTL_ARCH_ATOMIC_STORE_RELEASE_64(type, ptr, val) \
127  EASTL_ATOMIC_CPU_MB(); \
128  EASTL_ARCH_ATOMIC_ARM_STORE_64(type, ptr, val)
129 
130  #define EASTL_ARCH_ATOMIC_STORE_SEQ_CST_64(type, ptr, val) \
131  EASTL_ATOMIC_CPU_MB(); \
132  EASTL_ARCH_ATOMIC_ARM_STORE_64(type, ptr, val); \
133  EASTL_ATOMIC_CPU_MB()
134 
135 
136  #endif
137 
138 
139 #endif
140 
141 
142 #endif /* EASTL_ATOMIC_INTERNAL_ARCH_ARM_STORE_H */